version 1.26, 2001/09/11 01:30:31 |
version 1.27, 2001/09/11 08:56:47 |
|
|
* DEVELOPER SHALL HAVE NO LIABILITY IN CONNECTION WITH THE USE, |
* DEVELOPER SHALL HAVE NO LIABILITY IN CONNECTION WITH THE USE, |
* PERFORMANCE OR NON-PERFORMANCE OF THE SOFTWARE. |
* PERFORMANCE OR NON-PERFORMANCE OF THE SOFTWARE. |
* |
* |
* $OpenXM: OpenXM_contrib2/asir2000/builtin/gr.c,v 1.25 2001/09/10 05:55:14 noro Exp $ |
* $OpenXM: OpenXM_contrib2/asir2000/builtin/gr.c,v 1.26 2001/09/11 01:30:31 noro Exp $ |
*/ |
*/ |
#include "ca.h" |
#include "ca.h" |
#include "parse.h" |
#include "parse.h" |
#include "base.h" |
#include "base.h" |
#include "ox.h" |
#include "ox.h" |
|
|
|
#if defined(__GNUC__) |
|
#define INLINE inline |
|
#elif defined(VISUAL) |
|
#define INLINE __inline |
|
#else |
|
#define INLINE |
|
#endif |
|
|
#define ITOS(p) (((unsigned int)(p))&0x7fffffff) |
#define ITOS(p) (((unsigned int)(p))&0x7fffffff) |
#define STOI(i) ((P)((unsigned int)(i)|0x80000000)) |
#define STOI(i) ((P)((unsigned int)(i)|0x80000000)) |
|
|
|
|
NODE TraceList; |
NODE TraceList; |
NODE AllTraceList; |
NODE AllTraceList; |
|
|
int eqdl(nv,dl1,dl2) |
INLINE int eqdl(nv,dl1,dl2) |
int nv; |
int nv; |
DL dl1,dl2; |
DL dl1,dl2; |
{ |
{ |
|
|
struct order_spec *ord; |
struct order_spec *ord; |
LIST *rp; |
LIST *rp; |
{ |
{ |
int i,mindex,m,nochk; |
int i,mindex,m,nochk,homogen; |
struct order_spec ord1; |
struct order_spec ord1; |
VL fv,vv,vc; |
VL fv,vv,vc; |
NODE fd,fd0,fi,fi0,r,r0,t,subst,x,s,xx; |
NODE fd,fd0,fi,fi0,r,r0,t,subst,x,s,xx; |
|
|
if ( ord->id && NVars != ord->nv ) |
if ( ord->id && NVars != ord->nv ) |
error("dp_f4_main : invalid order specification"); |
error("dp_f4_main : invalid order specification"); |
initd(ord); |
initd(ord); |
for ( fd0 = 0, t = BDY(f); t; t = NEXT(t) ) { |
for ( fd0 = 0, t = BDY(f), homogen = 1; t; t = NEXT(t) ) { |
NEXTNODE(fd0,fd); ptod(CO,vv,(P)BDY(t),(DP *)&BDY(fd)); |
NEXTNODE(fd0,fd); ptod(CO,vv,(P)BDY(t),(DP *)&BDY(fd)); |
|
if ( homogen ) |
|
homogen = dp_homogeneous(BDY(fd)); |
} |
} |
if ( fd0 ) NEXT(fd) = 0; |
if ( fd0 ) NEXT(fd) = 0; |
setup_arrays(fd0,0,&s); |
setup_arrays(fd0,0,&s); |
x = gb_f4(s); |
x = gb_f4(s); |
reduceall(x,&xx); x = xx; |
if ( !homogen ) { |
|
reduceall(x,&xx); x = xx; |
|
} |
for ( r0 = 0; x; x = NEXT(x) ) { |
for ( r0 = 0; x; x = NEXT(x) ) { |
NEXTNODE(r0,r); dp_load((int)BDY(x),&ps[(int)BDY(x)]); |
NEXTNODE(r0,r); dp_load((int)BDY(x),&ps[(int)BDY(x)]); |
dtop(CO,vv,ps[(int)BDY(x)],(P *)&BDY(r)); |
dtop(CO,vv,ps[(int)BDY(x)],(P *)&BDY(r)); |
|
|
struct order_spec *ord; |
struct order_spec *ord; |
LIST *rp; |
LIST *rp; |
{ |
{ |
int i; |
int i,homogen; |
struct order_spec ord1; |
struct order_spec ord1; |
VL fv,vv,vc; |
VL fv,vv,vc; |
DP b,c,c1; |
DP b,c,c1; |
|
|
if ( ord->id && NVars != ord->nv ) |
if ( ord->id && NVars != ord->nv ) |
error("dp_f4_mod_main : invalid order specification"); |
error("dp_f4_mod_main : invalid order specification"); |
initd(ord); |
initd(ord); |
for ( fd0 = 0, t = BDY(f); t; t = NEXT(t) ) { |
for ( fd0 = 0, t = BDY(f), homogen = 1; t; t = NEXT(t) ) { |
ptod(CO,vv,(P)BDY(t),&b); |
ptod(CO,vv,(P)BDY(t),&b); |
|
if ( homogen ) |
|
homogen = dp_homogeneous(b); |
_dp_mod(b,m,0,&c); |
_dp_mod(b,m,0,&c); |
_dp_monic(c,m,&c1); |
_dp_monic(c,m,&c1); |
if ( c ) { |
if ( c ) { |
|
|
if ( fd0 ) NEXT(fd) = 0; |
if ( fd0 ) NEXT(fd) = 0; |
setup_arrays(fd0,m,&s); |
setup_arrays(fd0,m,&s); |
x = gb_f4_mod(s,m); |
x = gb_f4_mod(s,m); |
reduceall_mod(x,m,&xx); x = xx; |
if ( !homogen ) { |
|
reduceall_mod(x,m,&xx); x = xx; |
|
} |
for ( r0 = 0; x; x = NEXT(x) ) { |
for ( r0 = 0; x; x = NEXT(x) ) { |
NEXTNODE(r0,r); _dtop_mod(CO,vv,ps[(int)BDY(x)],(P *)&BDY(r)); |
NEXTNODE(r0,r); _dtop_mod(CO,vv,ps[(int)BDY(x)],(P *)&BDY(r)); |
} |
} |
|
|
} |
} |
} |
} |
#endif |
#endif |
fprintf(stderr,"\n"); |
|
|
|
get_eg(&tmp1); add_eg(&eg_symb,&tmp0,&tmp1); |
get_eg(&tmp1); add_eg(&eg_symb,&tmp0,&tmp1); |
init_eg(&eg_split_symb); add_eg(&eg_split_symb,&tmp0,&tmp1); |
init_eg(&eg_split_symb); add_eg(&eg_split_symb,&tmp0,&tmp1); |
|
|