| version 1.1, 2000/09/09 14:13:19 |
version 1.1.1.2, 2003/08/25 16:06:38 |
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| dnl Alpha time stamp counter access routine. |
dnl Alpha time stamp counter access routine. |
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| dnl Copyright (C) 2000 Free Software Foundation, Inc. |
dnl Copyright 2000 Free Software Foundation, Inc. |
| dnl |
dnl |
| dnl This file is part of the GNU MP Library. |
dnl This file is part of the GNU MP Library. |
| dnl |
dnl |
| Line 24 include(`../config.m4') |
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| Line 24 include(`../config.m4') |
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| C void speed_cyclecounter (unsigned int p[2]); |
C void speed_cyclecounter (unsigned int p[2]); |
| C |
C |
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C The rpcc instruction returns a 64-bit value split into two 32-bit fields. |
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C The lower 32 bits are set by the hardware, and the upper 32 bits are set |
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C by the operating system. The real per-process cycle count is the sum of |
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C these halves. |
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C Unfortunately, some operating systems don't get this right. NetBSD 1.3 is |
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C known to sometimes put garbage in the upper half. Whether newer NetBSD |
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C versions get it right, is unknown to us. |
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| C rpcc measures cycles elapsed in the user program and hence should be very |
C rpcc measures cycles elapsed in the user program and hence should be very |
| C accurate even on a busy system. Losing cache contents due to task |
C accurate even on a busy system. Losing cache contents due to task |
| C switching may have an effect though. |
C switching may have an effect though. |
| Line 31 C switching may have an effect though. |
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| Line 41 C switching may have an effect though. |
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| ASM_START() |
ASM_START() |
| PROLOGUE(speed_cyclecounter) |
PROLOGUE(speed_cyclecounter) |
| rpcc r0 |
rpcc r0 |
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srl r0,32,r1 |
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addq r1,r0,r0 |
| stl r0,0(r16) |
stl r0,0(r16) |
| srl r0,32,r0 |
stl r31,4(r16) C zero upper return word |
| stl r0,4(r16) |
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| ret r31,(r26),1 |
ret r31,(r26),1 |
| EPILOGUE(speed_cyclecounter) |
EPILOGUE(speed_cyclecounter) |
| ASM_END() |
ASM_END() |