| version 1.1.1.1, 2000/01/10 15:35:22 |
version 1.1.1.3, 2003/08/25 16:06:00 |
|
|
| /* longlong.h -- definitions for mixed size 32/64 bit arithmetic. |
/* longlong.h -- definitions for mixed size 32/64 bit arithmetic. |
| |
|
| Copyright (C) 1991, 1992, 1993, 1994, 1996 Free Software Foundation, Inc. |
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002 Free |
| |
Software Foundation, Inc. |
| |
|
| This file is free software; you can redistribute it and/or modify |
This file is free software; you can redistribute it and/or modify |
| it under the terms of the GNU Library General Public License as published by |
it under the terms of the GNU Lesser General Public License as published by |
| the Free Software Foundation; either version 2 of the License, or (at your |
the Free Software Foundation; either version 2.1 of the License, or (at your |
| option) any later version. |
option) any later version. |
| |
|
| This file is distributed in the hope that it will be useful, but |
This file is distributed in the hope that it will be useful, but |
| WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public |
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public |
| License for more details. |
License for more details. |
| |
|
| You should have received a copy of the GNU Library General Public License |
You should have received a copy of the GNU Lesser General Public License |
| along with this file; see the file COPYING.LIB. If not, write to |
along with this file; see the file COPYING.LIB. If not, write to |
| the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
| MA 02111-1307, USA. */ |
MA 02111-1307, USA. */ |
| Line 42 MA 02111-1307, USA. */ |
|
| Line 43 MA 02111-1307, USA. */ |
|
| #define __MPN(x) __##x |
#define __MPN(x) __##x |
| #endif |
#endif |
| |
|
| |
#ifndef _PROTO |
| |
#if (__STDC__-0) || defined (__cplusplus) |
| |
#define _PROTO(x) x |
| |
#else |
| |
#define _PROTO(x) () |
| |
#endif |
| |
#endif |
| |
|
| /* Define auxiliary asm macros. |
/* Define auxiliary asm macros. |
| |
|
| 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two |
1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two |
| Line 92 MA 02111-1307, USA. */ |
|
| Line 101 MA 02111-1307, USA. */ |
|
| Please add support for more CPUs here, or improve the current support |
Please add support for more CPUs here, or improve the current support |
| for the CPUs below! */ |
for the CPUs below! */ |
| |
|
| #if defined (__GNUC__) && !defined (NO_ASM) |
/* FIXME: The macros using external routines like __MPN(count_leading_zeros) |
| |
don't need to be under !NO_ASM */ |
| |
#if ! defined (NO_ASM) |
| |
|
| |
#if defined (__alpha) && W_TYPE_SIZE == 64 |
| |
/* Most alpha-based machines, except Cray systems. */ |
| |
#if defined (__GNUC__) |
| |
#define umul_ppmm(ph, pl, m0, m1) \ |
| |
do { \ |
| |
UDItype __m0 = (m0), __m1 = (m1); \ |
| |
__asm__ ("umulh %r1,%2,%0" \ |
| |
: "=r" (ph) \ |
| |
: "%rJ" (m0), "rI" (m1)); \ |
| |
(pl) = __m0 * __m1; \ |
| |
} while (0) |
| |
#define UMUL_TIME 18 |
| |
#else /* ! __GNUC__ */ |
| |
#include <machine/builtins.h> |
| |
#define umul_ppmm(ph, pl, m0, m1) \ |
| |
do { \ |
| |
UDItype __m0 = (m0), __m1 = (m1); \ |
| |
(ph) = __UMULH (m0, m1); \ |
| |
(pl) = __m0 * __m1; \ |
| |
} while (0) |
| |
#endif |
| |
#ifndef LONGLONG_STANDALONE |
| |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| |
do { UWtype __di; \ |
| |
__di = __MPN(invert_limb) (d); \ |
| |
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \ |
| |
} while (0) |
| |
#define UDIV_PREINV_ALWAYS 1 |
| |
#define UDIV_NEEDS_NORMALIZATION 1 |
| |
#define UDIV_TIME 220 |
| |
#endif /* LONGLONG_STANDALONE */ |
| |
/* clz_tab is required by mpn/alpha/cntlz.asm, and that file is built for |
| |
all alphas, even though ev67 and ev68 don't need it. */ |
| |
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB |
| |
#if defined (__GNUC__) && (HAVE_HOST_CPU_alphaev67 || HAVE_HOST_CPU_alphaev68) |
| |
#define count_leading_zeros(COUNT,X) \ |
| |
__asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X)) |
| |
#define count_trailing_zeros(COUNT,X) \ |
| |
__asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X)) |
| |
#else /* ! (ev67 || ev68) */ |
| |
#ifndef LONGLONG_STANDALONE |
| |
#if HAVE_ATTRIBUTE_CONST |
| |
long __MPN(count_leading_zeros) _PROTO ((UDItype)) __attribute__ ((const)); |
| |
#else |
| |
long __MPN(count_leading_zeros) _PROTO ((UDItype)); |
| |
#endif |
| |
#define count_leading_zeros(count, x) \ |
| |
((count) = __MPN(count_leading_zeros) (x)) |
| |
#endif /* LONGLONG_STANDALONE */ |
| |
#endif /* ! (ev67 || ev68) */ |
| |
#endif /* __alpha */ |
| |
|
| |
#if defined (_CRAY) && W_TYPE_SIZE == 64 |
| |
#include <intrinsics.h> |
| |
#define UDIV_PREINV_ALWAYS 1 |
| |
#define UDIV_NEEDS_NORMALIZATION 1 |
| |
#define UDIV_TIME 220 |
| |
long __MPN(count_leading_zeros) _PROTO ((UDItype)); |
| |
#define count_leading_zeros(count, x) \ |
| |
((count) = _leadz ((UWtype) (x))) |
| |
#if defined (_CRAYIEEE) /* I.e., Cray T90/ieee, T3D, and T3E */ |
| |
#define umul_ppmm(ph, pl, m0, m1) \ |
| |
do { \ |
| |
UDItype __m0 = (m0), __m1 = (m1); \ |
| |
(ph) = _int_mult_upper (m0, m1); \ |
| |
(pl) = __m0 * __m1; \ |
| |
} while (0) |
| |
#ifndef LONGLONG_STANDALONE |
| |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| |
do { UWtype __di; \ |
| |
__di = __MPN(invert_limb) (d); \ |
| |
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \ |
| |
} while (0) |
| |
#endif /* LONGLONG_STANDALONE */ |
| |
#endif /* _CRAYIEEE */ |
| |
#endif /* _CRAY */ |
| |
|
| |
#if defined (__hppa) && W_TYPE_SIZE == 64 |
| |
#if defined (__GNUC__) |
| |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ("add %4,%5,%1\n\tadd,dc %2,%3,%0" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "%rM" (ah), "rM" (bh), "%rM" (al), "rM" (bl)) |
| |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ("sub %4,%5,%1\n\tsub,db %2,%3,%0" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "rM" (ah), "rM" (bh), "rM" (al), "rM" (bl)) |
| |
#endif |
| |
/* We put the result pointer parameter last here, since it makes passing |
| |
of the other parameters more efficient. */ |
| |
#ifndef LONGLONG_STANDALONE |
| |
#define umul_ppmm(wh, wl, u, v) \ |
| |
do { \ |
| |
UWtype __p0; \ |
| |
(wh) = __MPN(umul_ppmm) (u, v, &__p0); \ |
| |
(wl) = __p0; \ |
| |
} while (0) |
| |
extern UWtype __MPN(umul_ppmm) _PROTO ((UWtype, UWtype, UWtype *)); |
| |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| |
do { UWtype __r; \ |
| |
(q) = __MPN(udiv_qrnnd) (n1, n0, d, &__r); \ |
| |
(r) = __r; \ |
| |
} while (0) |
| |
extern UWtype __MPN(udiv_qrnnd) _PROTO ((UWtype, UWtype, UWtype, UWtype *)); |
| |
#define UMUL_TIME 8 |
| |
#define UDIV_TIME 60 |
| |
#endif /* LONGLONG_STANDALONE */ |
| |
#endif /* hppa */ |
| |
|
| |
#if defined (__ia64) && W_TYPE_SIZE == 64 |
| |
#if defined (__GNUC__) |
| |
#define umul_ppmm(ph, pl, m0, m1) \ |
| |
do { \ |
| |
UDItype __m0 = (m0), __m1 = (m1); \ |
| |
__asm__ ("xma.hu %0 = %1, %2, f0" \ |
| |
: "=f" (ph) \ |
| |
: "f" (m0), "f" (m1)); \ |
| |
(pl) = __m0 * __m1; \ |
| |
} while (0) |
| |
#define UMUL_TIME 14 |
| |
#define count_leading_zeros(count, x) \ |
| |
do { \ |
| |
UWtype _x = (x), _y, _a, _c; \ |
| |
__asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \ |
| |
__asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \ |
| |
_c = (_a - 1) << 3; \ |
| |
_x >>= _c; \ |
| |
if (_x >= 1 << 4) \ |
| |
_x >>= 4, _c += 4; \ |
| |
if (_x >= 1 << 2) \ |
| |
_x >>= 2, _c += 2; \ |
| |
_c += _x >> 1; \ |
| |
(count) = W_TYPE_SIZE - 1 - _c; \ |
| |
} while (0) |
| |
#endif |
| |
#ifndef LONGLONG_STANDALONE |
| |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| |
do { UWtype __di; \ |
| |
__di = __MPN(invert_limb) (d); \ |
| |
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \ |
| |
} while (0) |
| |
#define UDIV_PREINV_ALWAYS 1 |
| |
#define UDIV_NEEDS_NORMALIZATION 1 |
| |
#endif |
| |
#define UDIV_TIME 220 |
| |
#endif |
| |
|
| |
|
| |
#if defined (__GNUC__) |
| |
|
| /* We sometimes need to clobber "cc" with gcc2, but that would not be |
/* We sometimes need to clobber "cc" with gcc2, but that would not be |
| understood by gcc1. Use cpp to avoid major code duplication. */ |
understood by gcc1. Use cpp to avoid major code duplication. */ |
| #if __GNUC__ < 2 |
#if __GNUC__ < 2 |
| Line 106 MA 02111-1307, USA. */ |
|
| Line 267 MA 02111-1307, USA. */ |
|
| |
|
| #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32 |
#if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("add %1,%4,%5 |
__asm__ ("add %1,%4,%5\n\taddc %0,%2,%3" \ |
| addc %0,%2,%3" \ |
: "=r" (sh), "=&r" (sl) \ |
| : "=r" ((USItype)(sh)), \ |
: "%r" (ah), "rI" (bh), "%r" (al), "rI" (bl)) |
| "=&r" ((USItype)(sl)) \ |
|
| : "%r" ((USItype)(ah)), \ |
|
| "rI" ((USItype)(bh)), \ |
|
| "%r" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("sub %1,%4,%5 |
__asm__ ("sub %1,%4,%5\n\tsubc %0,%2,%3" \ |
| subc %0,%2,%3" \ |
: "=r" (sh), "=&r" (sl) \ |
| : "=r" ((USItype)(sh)), \ |
: "r" (ah), "rI" (bh), "r" (al), "rI" (bl)) |
| "=&r" ((USItype)(sl)) \ |
|
| : "r" ((USItype)(ah)), \ |
|
| "rI" ((USItype)(bh)), \ |
|
| "r" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl))) |
|
| #define umul_ppmm(xh, xl, m0, m1) \ |
#define umul_ppmm(xh, xl, m0, m1) \ |
| do { \ |
do { \ |
| USItype __m0 = (m0), __m1 = (m1); \ |
USItype __m0 = (m0), __m1 = (m1); \ |
| __asm__ ("multiplu %0,%1,%2" \ |
__asm__ ("multiplu %0,%1,%2" \ |
| : "=r" ((USItype)(xl)) \ |
: "=r" (xl) \ |
| : "r" (__m0), \ |
: "r" (__m0), "r" (__m1)); \ |
| "r" (__m1)); \ |
|
| __asm__ ("multmu %0,%1,%2" \ |
__asm__ ("multmu %0,%1,%2" \ |
| : "=r" ((USItype)(xh)) \ |
: "=r" (xh) \ |
| : "r" (__m0), \ |
: "r" (__m0), "r" (__m1)); \ |
| "r" (__m1)); \ |
|
| } while (0) |
} while (0) |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| __asm__ ("dividu %0,%3,%4" \ |
__asm__ ("dividu %0,%3,%4" \ |
| : "=r" ((USItype)(q)), \ |
: "=r" (q), "=q" (r) \ |
| "=q" ((USItype)(r)) \ |
: "1" (n1), "r" (n0), "r" (d)) |
| : "1" ((USItype)(n1)), \ |
|
| "r" ((USItype)(n0)), \ |
|
| "r" ((USItype)(d))) |
|
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| __asm__ ("clz %0,%1" \ |
__asm__ ("clz %0,%1" \ |
| : "=r" ((USItype)(count)) \ |
: "=r" (count) \ |
| : "r" ((USItype)(x))) |
: "r" (x)) |
| #define COUNT_LEADING_ZEROS_0 32 |
#define COUNT_LEADING_ZEROS_0 32 |
| #endif /* __a29k__ */ |
#endif /* __a29k__ */ |
| |
|
| #if defined (__alpha) && W_TYPE_SIZE == 64 |
#if defined (__arc__) |
| #define umul_ppmm(ph, pl, m0, m1) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ("add.f\t%1, %4, %5\n\tadc\t%0, %2, %3" \ |
| |
: "=r" ((USItype) (sh)), \ |
| |
"=&r" ((USItype) (sl)) \ |
| |
: "%r" ((USItype) (ah)), \ |
| |
"rIJ" ((USItype) (bh)), \ |
| |
"%r" ((USItype) (al)), \ |
| |
"rIJ" ((USItype) (bl))) |
| |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ("sub.f\t%1, %4, %5\n\tsbc\t%0, %2, %3" \ |
| |
: "=r" ((USItype) (sh)), \ |
| |
"=&r" ((USItype) (sl)) \ |
| |
: "r" ((USItype) (ah)), \ |
| |
"rIJ" ((USItype) (bh)), \ |
| |
"r" ((USItype) (al)), \ |
| |
"rIJ" ((USItype) (bl))) |
| |
#endif |
| |
|
| |
#if defined (__arm__) && W_TYPE_SIZE == 32 |
| |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ("adds\t%1, %4, %5\n\tadc\t%0, %2, %3" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "%r" (ah), "rI" (bh), "%r" (al), "rI" (bl) __CLOBBER_CC) |
| |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| do { \ |
do { \ |
| UDItype __m0 = (m0), __m1 = (m1); \ |
if (__builtin_constant_p (al)) \ |
| __asm__ ("umulh %r1,%2,%0" \ |
{ \ |
| : "=r" ((UDItype) ph) \ |
if (__builtin_constant_p (ah)) \ |
| : "%rJ" (__m0), \ |
__asm__ ("rsbs\t%1, %5, %4\n\trsc\t%0, %3, %2" \ |
| "rI" (__m1)); \ |
: "=r" (sh), "=&r" (sl) \ |
| (pl) = __m0 * __m1; \ |
: "rI" (ah), "r" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \ |
| } while (0) |
else \ |
| #define UMUL_TIME 46 |
__asm__ ("rsbs\t%1, %5, %4\n\tsbc\t%0, %2, %3" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "r" (ah), "rI" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \ |
| |
} \ |
| |
else if (__builtin_constant_p (ah)) \ |
| |
{ \ |
| |
if (__builtin_constant_p (bl)) \ |
| |
__asm__ ("subs\t%1, %4, %5\n\trsc\t%0, %3, %2" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "rI" (ah), "r" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \ |
| |
else \ |
| |
__asm__ ("rsbs\t%1, %5, %4\n\trsc\t%0, %3, %2" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "rI" (ah), "r" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \ |
| |
} \ |
| |
else if (__builtin_constant_p (bl)) \ |
| |
{ \ |
| |
if (__builtin_constant_p (bh)) \ |
| |
__asm__ ("subs\t%1, %4, %5\n\tsbc\t%0, %2, %3" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "r" (ah), "rI" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \ |
| |
else \ |
| |
__asm__ ("subs\t%1, %4, %5\n\trsc\t%0, %3, %2" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "rI" (ah), "r" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \ |
| |
} \ |
| |
else /* only bh might be a constant */ \ |
| |
__asm__ ("subs\t%1, %4, %5\n\tsbc\t%0, %2, %3" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "r" (ah), "rI" (bh), "r" (al), "rI" (bl) __CLOBBER_CC);\ |
| |
} while (0) |
| |
#if 1 || defined (__arm_m__) /* `M' series has widening multiply support */ |
| |
#define umul_ppmm(xh, xl, a, b) \ |
| |
__asm__ ("umull %0,%1,%2,%3" : "=&r" (xl), "=&r" (xh) : "r" (a), "r" (b)) |
| |
#define UMUL_TIME 5 |
| |
#define smul_ppmm(xh, xl, a, b) \ |
| |
__asm__ ("smull %0,%1,%2,%3" : "=&r" (xl), "=&r" (xh) : "r" (a), "r" (b)) |
| #ifndef LONGLONG_STANDALONE |
#ifndef LONGLONG_STANDALONE |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| do { UDItype __r; \ |
do { UWtype __di; \ |
| (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ |
__di = __MPN(invert_limb) (d); \ |
| (r) = __r; \ |
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \ |
| } while (0) |
} while (0) |
| extern UDItype __udiv_qrnnd (); |
#define UDIV_PREINV_ALWAYS 1 |
| #define UDIV_TIME 220 |
#define UDIV_NEEDS_NORMALIZATION 1 |
| |
#define UDIV_TIME 70 |
| #endif /* LONGLONG_STANDALONE */ |
#endif /* LONGLONG_STANDALONE */ |
| #endif /* __alpha */ |
#else |
| |
|
| #if defined (__arm__) && W_TYPE_SIZE == 32 |
|
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
|
| __asm__ ("adds %1, %4, %5 |
|
| adc %0, %2, %3" \ |
|
| : "=r" ((USItype)(sh)), \ |
|
| "=&r" ((USItype)(sl)) \ |
|
| : "%r" ((USItype)(ah)), \ |
|
| "rI" ((USItype)(bh)), \ |
|
| "%r" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
|
| __asm__ ("subs %1, %4, %5 |
|
| sbc %0, %2, %3" \ |
|
| : "=r" ((USItype)(sh)), \ |
|
| "=&r" ((USItype)(sl)) \ |
|
| : "r" ((USItype)(ah)), \ |
|
| "rI" ((USItype)(bh)), \ |
|
| "r" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl))) |
|
| #define umul_ppmm(xh, xl, a, b) \ |
#define umul_ppmm(xh, xl, a, b) \ |
| __asm__ ("%@ Inlined umul_ppmm |
__asm__ ("%@ Inlined umul_ppmm\n" \ |
| mov %|r0, %2, lsr #16 |
" mov %|r0, %2, lsr #16\n" \ |
| mov %|r2, %3, lsr #16 |
" mov %|r2, %3, lsr #16\n" \ |
| bic %|r1, %2, %|r0, lsl #16 |
" bic %|r1, %2, %|r0, lsl #16\n" \ |
| bic %|r2, %3, %|r2, lsl #16 |
" bic %|r2, %3, %|r2, lsl #16\n" \ |
| mul %1, %|r1, %|r2 |
" mul %1, %|r1, %|r2\n" \ |
| mul %|r2, %|r0, %|r2 |
" mul %|r2, %|r0, %|r2\n" \ |
| mul %|r1, %0, %|r1 |
" mul %|r1, %0, %|r1\n" \ |
| mul %0, %|r0, %0 |
" mul %0, %|r0, %0\n" \ |
| adds %|r1, %|r2, %|r1 |
" adds %|r1, %|r2, %|r1\n" \ |
| addcs %0, %0, #65536 |
" addcs %0, %0, #65536\n" \ |
| adds %1, %1, %|r1, lsl #16 |
" adds %1, %1, %|r1, lsl #16\n" \ |
| adc %0, %0, %|r1, lsr #16" \ |
" adc %0, %0, %|r1, lsr #16" \ |
| : "=&r" ((USItype)(xh)), \ |
: "=&r" (xh), "=r" (xl) \ |
| "=r" ((USItype)(xl)) \ |
: "r" (a), "r" (b) \ |
| : "r" ((USItype)(a)), \ |
|
| "r" ((USItype)(b)) \ |
|
| : "r0", "r1", "r2") |
: "r0", "r1", "r2") |
| #define UMUL_TIME 20 |
#define UMUL_TIME 20 |
| #define UDIV_TIME 100 |
#ifndef LONGLONG_STANDALONE |
| |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| |
do { UWtype __r; \ |
| |
(q) = __MPN(udiv_qrnnd) (&__r, (n1), (n0), (d)); \ |
| |
(r) = __r; \ |
| |
} while (0) |
| |
extern UWtype __MPN(udiv_qrnnd) _PROTO ((UWtype *, UWtype, UWtype, UWtype)); |
| |
#define UDIV_TIME 200 |
| |
#endif /* LONGLONG_STANDALONE */ |
| |
#endif |
| #endif /* __arm__ */ |
#endif /* __arm__ */ |
| |
|
| #if defined (__clipper__) && W_TYPE_SIZE == 32 |
#if defined (__clipper__) && W_TYPE_SIZE == 32 |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| ({union {UDItype __ll; \ |
({union {UDItype __ll; \ |
| struct {USItype __l, __h;} __i; \ |
struct {USItype __l, __h;} __i; \ |
| } __xx; \ |
} __x; \ |
| __asm__ ("mulwux %2,%0" \ |
__asm__ ("mulwux %2,%0" \ |
| : "=r" (__xx.__ll) \ |
: "=r" (__x.__ll) \ |
| : "%0" ((USItype)(u)), \ |
: "%0" ((USItype)(u)), "r" ((USItype)(v))); \ |
| "r" ((USItype)(v))); \ |
(w1) = __x.__i.__h; (w0) = __x.__i.__l;}) |
| (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) |
|
| #define smul_ppmm(w1, w0, u, v) \ |
#define smul_ppmm(w1, w0, u, v) \ |
| ({union {DItype __ll; \ |
({union {DItype __ll; \ |
| struct {SItype __l, __h;} __i; \ |
struct {SItype __l, __h;} __i; \ |
| } __xx; \ |
} __x; \ |
| __asm__ ("mulwx %2,%0" \ |
__asm__ ("mulwx %2,%0" \ |
| : "=r" (__xx.__ll) \ |
: "=r" (__x.__ll) \ |
| : "%0" ((SItype)(u)), \ |
: "%0" ((SItype)(u)), "r" ((SItype)(v))); \ |
| "r" ((SItype)(v))); \ |
(w1) = __x.__i.__h; (w0) = __x.__i.__l;}) |
| (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) |
|
| #define __umulsidi3(u, v) \ |
#define __umulsidi3(u, v) \ |
| ({UDItype __w; \ |
({UDItype __w; \ |
| __asm__ ("mulwux %2,%0" \ |
__asm__ ("mulwux %2,%0" \ |
| : "=r" (__w) \ |
: "=r" (__w) : "%0" ((USItype)(u)), "r" ((USItype)(v))); \ |
| : "%0" ((USItype)(u)), \ |
|
| "r" ((USItype)(v))); \ |
|
| __w; }) |
__w; }) |
| #endif /* __clipper__ */ |
#endif /* __clipper__ */ |
| |
|
| |
/* Fujitsu vector computers. */ |
| |
#if defined (__uxp__) && W_TYPE_SIZE == 32 |
| |
#define umul_ppmm(ph, pl, u, v) \ |
| |
do { \ |
| |
union {UDItype __ll; \ |
| |
struct {USItype __h, __l;} __i; \ |
| |
} __x; \ |
| |
__asm__ ("mult.lu %1,%2,%0" : "=r" (__x.__ll) : "%r" (u), "rK" (v));\ |
| |
(ph) = __x.__i.__h; \ |
| |
(pl) = __x.__i.__l; \ |
| |
} while (0) |
| |
#define smul_ppmm(ph, pl, u, v) \ |
| |
do { \ |
| |
union {UDItype __ll; \ |
| |
struct {USItype __h, __l;} __i; \ |
| |
} __x; \ |
| |
__asm__ ("mult.l %1,%2,%0" : "=r" (__x.__ll) : "%r" (u), "rK" (v)); \ |
| |
(ph) = __x.__i.__h; \ |
| |
(pl) = __x.__i.__l; \ |
| |
} while (0) |
| |
#endif |
| |
|
| #if defined (__gmicro__) && W_TYPE_SIZE == 32 |
#if defined (__gmicro__) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("add.w %5,%1 |
__asm__ ("add.w %5,%1\n\taddx %3,%0" \ |
| addx %3,%0" \ |
: "=g" ((USItype)(sh)), "=&g" ((USItype)(sl)) \ |
| : "=g" ((USItype)(sh)), \ |
: "%0" ((USItype)(ah)), "g" ((USItype)(bh)), \ |
| "=&g" ((USItype)(sl)) \ |
"%1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "%0" ((USItype)(ah)), \ |
|
| "g" ((USItype)(bh)), \ |
|
| "%1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("sub.w %5,%1 |
__asm__ ("sub.w %5,%1\n\tsubx %3,%0" \ |
| subx %3,%0" \ |
: "=g" ((USItype)(sh)), "=&g" ((USItype)(sl)) \ |
| : "=g" ((USItype)(sh)), \ |
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \ |
| "=&g" ((USItype)(sl)) \ |
"1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "0" ((USItype)(ah)), \ |
|
| "g" ((USItype)(bh)), \ |
|
| "1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| #define umul_ppmm(ph, pl, m0, m1) \ |
#define umul_ppmm(ph, pl, m0, m1) \ |
| __asm__ ("mulx %3,%0,%1" \ |
__asm__ ("mulx %3,%0,%1" \ |
| : "=g" ((USItype)(ph)), \ |
: "=g" ((USItype)(ph)), "=r" ((USItype)(pl)) \ |
| "=r" ((USItype)(pl)) \ |
: "%0" ((USItype)(m0)), "g" ((USItype)(m1))) |
| : "%0" ((USItype)(m0)), \ |
|
| "g" ((USItype)(m1))) |
|
| #define udiv_qrnnd(q, r, nh, nl, d) \ |
#define udiv_qrnnd(q, r, nh, nl, d) \ |
| __asm__ ("divx %4,%0,%1" \ |
__asm__ ("divx %4,%0,%1" \ |
| : "=g" ((USItype)(q)), \ |
: "=g" ((USItype)(q)), "=r" ((USItype)(r)) \ |
| "=r" ((USItype)(r)) \ |
: "1" ((USItype)(nh)), "0" ((USItype)(nl)), "g" ((USItype)(d))) |
| : "1" ((USItype)(nh)), \ |
|
| "0" ((USItype)(nl)), \ |
|
| "g" ((USItype)(d))) |
|
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| __asm__ ("bsch/1 %1,%0" \ |
__asm__ ("bsch/1 %1,%0" \ |
| : "=g" (count) \ |
: "=g" (count) : "g" ((USItype)(x)), "0" ((USItype)0)) |
| : "g" ((USItype)(x)), \ |
|
| "0" ((USItype)0)) |
|
| #endif |
#endif |
| |
|
| #if defined (__hppa) && W_TYPE_SIZE == 32 |
#if defined (__hppa) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("add %4,%5,%1 |
__asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ |
| addc %2,%3,%0" \ |
: "=r" (sh), "=&r" (sl) \ |
| : "=r" ((USItype)(sh)), \ |
: "%rM" (ah), "rM" (bh), "%rM" (al), "rM" (bl)) |
| "=&r" ((USItype)(sl)) \ |
|
| : "%rM" ((USItype)(ah)), \ |
|
| "rM" ((USItype)(bh)), \ |
|
| "%rM" ((USItype)(al)), \ |
|
| "rM" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("sub %4,%5,%1 |
__asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \ |
| subb %2,%3,%0" \ |
: "=r" (sh), "=&r" (sl) \ |
| : "=r" ((USItype)(sh)), \ |
: "rM" (ah), "rM" (bh), "rM" (al), "rM" (bl)) |
| "=&r" ((USItype)(sl)) \ |
|
| : "rM" ((USItype)(ah)), \ |
|
| "rM" ((USItype)(bh)), \ |
|
| "rM" ((USItype)(al)), \ |
|
| "rM" ((USItype)(bl))) |
|
| #if defined (_PA_RISC1_1) |
#if defined (_PA_RISC1_1) |
| #define umul_ppmm(wh, wl, u, v) \ |
#define umul_ppmm(wh, wl, u, v) \ |
| do { \ |
do { \ |
| union {UDItype __ll; \ |
union {UDItype __ll; \ |
| struct {USItype __h, __l;} __i; \ |
struct {USItype __h, __l;} __i; \ |
| } __xx; \ |
} __x; \ |
| __asm__ ("xmpyu %1,%2,%0" \ |
__asm__ ("xmpyu %1,%2,%0" : "=*f" (__x.__ll) : "*f" (u), "*f" (v)); \ |
| : "=*f" (__xx.__ll) \ |
(wh) = __x.__i.__h; \ |
| : "*f" ((USItype)(u)), \ |
(wl) = __x.__i.__l; \ |
| "*f" ((USItype)(v))); \ |
|
| (wh) = __xx.__i.__h; \ |
|
| (wl) = __xx.__i.__l; \ |
|
| } while (0) |
} while (0) |
| #define UMUL_TIME 8 |
#define UMUL_TIME 8 |
| #define UDIV_TIME 60 |
#define UDIV_TIME 60 |
| Line 320 extern UDItype __udiv_qrnnd (); |
|
| Line 503 extern UDItype __udiv_qrnnd (); |
|
| #endif |
#endif |
| #ifndef LONGLONG_STANDALONE |
#ifndef LONGLONG_STANDALONE |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| do { USItype __r; \ |
do { UWtype __r; \ |
| (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ |
(q) = __MPN(udiv_qrnnd) (&__r, (n1), (n0), (d)); \ |
| (r) = __r; \ |
(r) = __r; \ |
| } while (0) |
} while (0) |
| extern USItype __udiv_qrnnd (); |
extern UWtype __MPN(udiv_qrnnd) _PROTO ((UWtype *, UWtype, UWtype, UWtype)); |
| #endif /* LONGLONG_STANDALONE */ |
#endif /* LONGLONG_STANDALONE */ |
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| do { \ |
do { \ |
| USItype __tmp; \ |
USItype __tmp; \ |
| __asm__ ( \ |
__asm__ ( \ |
| "ldi 1,%0 |
"ldi 1,%0\n" \ |
| extru,= %1,15,16,%%r0 ; Bits 31..16 zero? |
" extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \ |
| extru,tr %1,15,16,%1 ; No. Shift down, skip add. |
" extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \ |
| ldo 16(%0),%0 ; Yes. Perform add. |
" ldo 16(%0),%0 ; Yes. Perform add.\n" \ |
| extru,= %1,23,8,%%r0 ; Bits 15..8 zero? |
" extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \ |
| extru,tr %1,23,8,%1 ; No. Shift down, skip add. |
" extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \ |
| ldo 8(%0),%0 ; Yes. Perform add. |
" ldo 8(%0),%0 ; Yes. Perform add.\n" \ |
| extru,= %1,27,4,%%r0 ; Bits 7..4 zero? |
" extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \ |
| extru,tr %1,27,4,%1 ; No. Shift down, skip add. |
" extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \ |
| ldo 4(%0),%0 ; Yes. Perform add. |
" ldo 4(%0),%0 ; Yes. Perform add.\n" \ |
| extru,= %1,29,2,%%r0 ; Bits 3..2 zero? |
" extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \ |
| extru,tr %1,29,2,%1 ; No. Shift down, skip add. |
" extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \ |
| ldo 2(%0),%0 ; Yes. Perform add. |
" ldo 2(%0),%0 ; Yes. Perform add.\n" \ |
| extru %1,30,1,%1 ; Extract bit 1. |
" extru %1,30,1,%1 ; Extract bit 1.\n" \ |
| sub %0,%1,%0 ; Subtract it. |
" sub %0,%1,%0 ; Subtract it.\n" \ |
| " : "=r" (count), "=r" (__tmp) : "1" (x)); \ |
: "=r" (count), "=r" (__tmp) : "1" (x)); \ |
| } while (0) |
} while (0) |
| #endif /* hppa */ |
#endif /* hppa */ |
| |
|
| #if (defined (__i370__) || defined (__mvs__)) && W_TYPE_SIZE == 32 |
#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32 |
| #define umul_ppmm(xh, xl, m0, m1) \ |
|
| do { \ |
|
| union {UDItype __ll; \ |
|
| struct {USItype __h, __l;} __i; \ |
|
| } __xx; \ |
|
| USItype __m0 = (m0), __m1 = (m1); \ |
|
| __asm__ ("mr %0,%3" \ |
|
| : "=r" (__xx.__i.__h), \ |
|
| "=r" (__xx.__i.__l) \ |
|
| : "%1" (__m0), \ |
|
| "r" (__m1)); \ |
|
| (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ |
|
| (xh) += ((((SItype) __m0 >> 31) & __m1) \ |
|
| + (((SItype) __m1 >> 31) & __m0)); \ |
|
| } while (0) |
|
| #define smul_ppmm(xh, xl, m0, m1) \ |
#define smul_ppmm(xh, xl, m0, m1) \ |
| do { \ |
do { \ |
| union {DItype __ll; \ |
union {DItype __ll; \ |
| struct {USItype __h, __l;} __i; \ |
struct {USItype __h, __l;} __i; \ |
| } __xx; \ |
} __x; \ |
| __asm__ ("mr %0,%3" \ |
__asm__ ("lr %N0,%1\n\tmr %0,%2" \ |
| : "=r" (__xx.__i.__h), \ |
: "=&r" (__x.__ll) \ |
| "=r" (__xx.__i.__l) \ |
: "r" (m0), "r" (m1)); \ |
| : "%1" (m0), \ |
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \ |
| "r" (m1)); \ |
|
| (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ |
|
| } while (0) |
} while (0) |
| #define sdiv_qrnnd(q, r, n1, n0, d) \ |
#define sdiv_qrnnd(q, r, n1, n0, d) \ |
| do { \ |
do { \ |
| union {DItype __ll; \ |
union {DItype __ll; \ |
| struct {USItype __h, __l;} __i; \ |
struct {USItype __h, __l;} __i; \ |
| } __xx; \ |
} __x; \ |
| __xx.__i.__h = n1; __xx.__i.__l = n0; \ |
__x.__i.__h = n1; __x.__i.__l = n0; \ |
| __asm__ ("dr %0,%2" \ |
__asm__ ("dr %0,%2" \ |
| : "=r" (__xx.__ll) \ |
: "=r" (__x.__ll) \ |
| : "0" (__xx.__ll), "r" (d)); \ |
: "0" (__x.__ll), "r" (d)); \ |
| (q) = __xx.__i.__l; (r) = __xx.__i.__h; \ |
(q) = __x.__i.__l; (r) = __x.__i.__h; \ |
| } while (0) |
} while (0) |
| #endif |
#endif |
| |
|
| #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 |
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("addl %5,%1 |
__asm__ ("addl %5,%1\n\tadcl %3,%0" \ |
| adcl %3,%0" \ |
: "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \ |
| : "=r" ((USItype)(sh)), \ |
: "%0" ((USItype)(ah)), "g" ((USItype)(bh)), \ |
| "=&r" ((USItype)(sl)) \ |
"%1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "%0" ((USItype)(ah)), \ |
|
| "g" ((USItype)(bh)), \ |
|
| "%1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("subl %5,%1 |
__asm__ ("subl %5,%1\n\tsbbl %3,%0" \ |
| sbbl %3,%0" \ |
: "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \ |
| : "=r" ((USItype)(sh)), \ |
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \ |
| "=&r" ((USItype)(sl)) \ |
"1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "0" ((USItype)(ah)), \ |
|
| "g" ((USItype)(bh)), \ |
|
| "1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("mull %3" \ |
__asm__ ("mull %3" \ |
| : "=a" ((USItype)(w0)), \ |
: "=a" (w0), "=d" (w1) \ |
| "=d" ((USItype)(w1)) \ |
: "%0" ((USItype)(u)), "rm" ((USItype)(v))) |
| : "%0" ((USItype)(u)), \ |
#define udiv_qrnnd(q, r, n1, n0, dx) /* d renamed to dx avoiding "=d" */\ |
| "rm" ((USItype)(v))) |
__asm__ ("divl %4" /* stringification in K&R C */ \ |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
: "=a" (q), "=d" (r) \ |
| __asm__ ("divl %4" \ |
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "rm" ((USItype)(dx))) |
| : "=a" ((USItype)(q)), \ |
|
| "=d" ((USItype)(r)) \ |
/* P5 bsrl takes between 10 and 72 cycles depending where the most |
| : "0" ((USItype)(n0)), \ |
significant 1 bit is, hence the use of the alternatives below. bsfl is |
| "1" ((USItype)(n1)), \ |
slow too, between 18 and 42 depending where the least significant 1 bit |
| "rm" ((USItype)(d))) |
is. The faster count_leading_zeros are pressed into service via the |
| #define count_leading_zeros(count, x) \ |
generic count_trailing_zeros at the end of the file. */ |
| |
|
| |
#if HAVE_HOST_CPU_i586 || HAVE_HOST_CPU_pentium |
| |
|
| |
/* The following should be a fixed 14 cycles or so. Some scheduling |
| |
opportunities should be available between the float load/store too. This |
| |
is used (with "n&-n" to get trailing zeros) in gcc 3 for __builtin_ffs |
| |
and is apparently suggested by the Intel optimizing manual (don't know |
| |
exactly where). gcc 2.95 or up will be best for this, so the "double" is |
| |
correctly aligned on the stack. */ |
| |
|
| |
#define count_leading_zeros(c,n) \ |
| do { \ |
do { \ |
| |
union { \ |
| |
double d; \ |
| |
unsigned a[2]; \ |
| |
} __u; \ |
| |
ASSERT ((n) != 0); \ |
| |
__u.d = (UWtype) (n); \ |
| |
(c) = 0x3FF + 31 - (__u.a[1] >> 20); \ |
| |
} while (0) |
| |
#define COUNT_LEADING_ZEROS_0 (0x3FF + 31) |
| |
|
| |
#else /* ! pentium */ |
| |
#if HAVE_HOST_CPU_pentiummmx |
| |
|
| |
/* The following should be a fixed 14 or 15 cycles, but possibly plus an L1 |
| |
cache miss reading from __clz_tab. It's favoured over the float above so |
| |
as to avoid mixing MMX and x87, since the penalty for switching between |
| |
the two is about 100 cycles. |
| |
|
| |
The asm block sets __shift to -3 if the high 24 bits are clear, -2 for |
| |
16, -1 for 8, or 0 otherwise. This could be written equivalently as |
| |
follows, but as of gcc 2.95.2 it results in conditional jumps. |
| |
|
| |
__shift = -(__n < 0x1000000); |
| |
__shift -= (__n < 0x10000); |
| |
__shift -= (__n < 0x100); |
| |
|
| |
The middle two sbbl and cmpl's pair, and with luck something gcc |
| |
generates might pair with the first cmpl and the last sbbl. The "32+1" |
| |
constant could be folded into __clz_tab[], but it doesn't seem worth |
| |
making a different table just for that. */ |
| |
|
| |
#define count_leading_zeros(c,n) \ |
| |
do { \ |
| |
USItype __n = (n); \ |
| |
USItype __shift; \ |
| |
__asm__ ("cmpl $0x1000000, %1\n" \ |
| |
"sbbl %0, %0\n" \ |
| |
"cmpl $0x10000, %1\n" \ |
| |
"sbbl $0, %0\n" \ |
| |
"cmpl $0x100, %1\n" \ |
| |
"sbbl $0, %0\n" \ |
| |
: "=&r" (__shift) : "r" (__n)); \ |
| |
__shift = __shift*8 + 24 + 1; \ |
| |
(c) = 32 + 1 - __shift - __clz_tab[__n >> __shift]; \ |
| |
} while (0) |
| |
|
| |
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB |
| |
#define COUNT_LEADING_ZEROS_0 31 /* n==0 indistinguishable from n==1 */ |
| |
|
| |
#else /* !pentiummmx */ |
| |
/* On P6, gcc prior to 3.0 generates a partial register stall for |
| |
__cbtmp^31, due to using "xorb $31" instead of "xorl $31", the former |
| |
being 1 code byte smaller. "31-__cbtmp" is a workaround, probably at the |
| |
cost of one extra instruction. Do this for "i386" too, since that means |
| |
generic x86. */ |
| |
#if __GNUC__ < 3 \ |
| |
&& (HAVE_HOST_CPU_i386 \ |
| |
|| HAVE_HOST_CPU_i686 \ |
| |
|| HAVE_HOST_CPU_pentiumpro \ |
| |
|| HAVE_HOST_CPU_pentium2 \ |
| |
|| HAVE_HOST_CPU_pentium3) |
| |
#define count_leading_zeros(count, x) \ |
| |
do { \ |
| USItype __cbtmp; \ |
USItype __cbtmp; \ |
| __asm__ ("bsrl %1,%0" \ |
ASSERT ((x) != 0); \ |
| : "=r" (__cbtmp) : "rm" ((USItype)(x))); \ |
__asm__ ("bsrl %1,%0" : "=r" (__cbtmp) : "rm" ((USItype)(x))); \ |
| |
(count) = 31 - __cbtmp; \ |
| |
} while (0) |
| |
#else |
| |
#define count_leading_zeros(count, x) \ |
| |
do { \ |
| |
USItype __cbtmp; \ |
| |
ASSERT ((x) != 0); \ |
| |
__asm__ ("bsrl %1,%0" : "=r" (__cbtmp) : "rm" ((USItype)(x))); \ |
| (count) = __cbtmp ^ 31; \ |
(count) = __cbtmp ^ 31; \ |
| } while (0) |
} while (0) |
| #define count_trailing_zeros(count, x) \ |
#endif |
| __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x))) |
|
| |
#define count_trailing_zeros(count, x) \ |
| |
do { \ |
| |
ASSERT ((x) != 0); \ |
| |
__asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x))); \ |
| |
} while (0) |
| |
#endif /* ! pentiummmx */ |
| |
#endif /* ! pentium */ |
| |
|
| #ifndef UMUL_TIME |
#ifndef UMUL_TIME |
| #define UMUL_TIME 40 |
#define UMUL_TIME 10 |
| #endif |
#endif |
| #ifndef UDIV_TIME |
#ifndef UDIV_TIME |
| #define UDIV_TIME 40 |
#define UDIV_TIME 40 |
| #endif |
#endif |
| #endif /* 80x86 */ |
#endif /* 80x86 */ |
| |
|
| |
#if defined (__x86_64__) && W_TYPE_SIZE == 64 |
| |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ("addq %5,%1\n\tadcq %3,%0" \ |
| |
: "=r" ((UDItype)(sh)), "=&r" ((UDItype)(sl)) \ |
| |
: "%0" ((UDItype)(ah)), "g" ((UDItype)(bh)), \ |
| |
"%1" ((UDItype)(al)), "g" ((UDItype)(bl))) |
| |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ("subq %5,%1\n\tsbbq %3,%0" \ |
| |
: "=r" ((UDItype)(sh)), "=&r" ((UDItype)(sl)) \ |
| |
: "0" ((UDItype)(ah)), "g" ((UDItype)(bh)), \ |
| |
"1" ((UDItype)(al)), "g" ((UDItype)(bl))) |
| |
#define umul_ppmm(w1, w0, u, v) \ |
| |
__asm__ ("mulq %3" \ |
| |
: "=a" (w0), "=d" (w1) \ |
| |
: "%0" ((UDItype)(u)), "rm" ((UDItype)(v))) |
| |
#define udiv_qrnnd(q, r, n1, n0, dx) /* d renamed to dx avoiding "=d" */\ |
| |
__asm__ ("divq %4" /* stringification in K&R C */ \ |
| |
: "=a" (q), "=d" (r) \ |
| |
: "0" ((UDItype)(n0)), "1" ((UDItype)(n1)), "rm" ((UDItype)(dx))) |
| |
#define count_leading_zeros(count, x) \ |
| |
do { \ |
| |
UDItype __cbtmp; \ |
| |
ASSERT ((x) != 0); \ |
| |
__asm__ ("bsrq %1,%0" : "=r" (__cbtmp) : "rm" ((UDItype)(x))); \ |
| |
(count) = __cbtmp ^ 63; \ |
| |
} while (0) |
| |
#define count_trailing_zeros(count, x) \ |
| |
do { \ |
| |
ASSERT ((x) != 0); \ |
| |
__asm__ ("bsfq %1,%0" : "=r" (count) : "rm" ((UDItype)(x))); \ |
| |
} while (0) |
| |
#endif /* x86_64 */ |
| |
|
| #if defined (__i860__) && W_TYPE_SIZE == 32 |
#if defined (__i860__) && W_TYPE_SIZE == 32 |
| #define rshift_rhlc(r,h,l,c) \ |
#define rshift_rhlc(r,h,l,c) \ |
| __asm__ ("shr %3,r0,r0\;shrd %1,%2,%0" \ |
__asm__ ("shr %3,r0,r0\;shrd %1,%2,%0" \ |
| Line 448 extern USItype __udiv_qrnnd (); |
|
| Line 729 extern USItype __udiv_qrnnd (); |
|
| #if defined (__i960__) && W_TYPE_SIZE == 32 |
#if defined (__i960__) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("cmpo 1,0\;addc %5,%4,%1\;addc %3,%2,%0" \ |
__asm__ ("cmpo 1,0\;addc %5,%4,%1\;addc %3,%2,%0" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) \ |
| "=&r" ((USItype)(sl)) \ |
: "%dI" (ah), "dI" (bh), "%dI" (al), "dI" (bl)) |
| : "%dI" ((USItype)(ah)), \ |
|
| "dI" ((USItype)(bh)), \ |
|
| "%dI" ((USItype)(al)), \ |
|
| "dI" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("cmpo 0,0\;subc %5,%4,%1\;subc %3,%2,%0" \ |
__asm__ ("cmpo 0,0\;subc %5,%4,%1\;subc %3,%2,%0" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) \ |
| "=&r" ((USItype)(sl)) \ |
: "dI" (ah), "dI" (bh), "dI" (al), "dI" (bl)) |
| : "dI" ((USItype)(ah)), \ |
|
| "dI" ((USItype)(bh)), \ |
|
| "dI" ((USItype)(al)), \ |
|
| "dI" ((USItype)(bl))) |
|
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| ({union {UDItype __ll; \ |
({union {UDItype __ll; \ |
| struct {USItype __l, __h;} __i; \ |
struct {USItype __l, __h;} __i; \ |
| } __xx; \ |
} __x; \ |
| __asm__ ("emul %2,%1,%0" \ |
__asm__ ("emul %2,%1,%0" \ |
| : "=d" (__xx.__ll) \ |
: "=d" (__x.__ll) : "%dI" (u), "dI" (v)); \ |
| : "%dI" ((USItype)(u)), \ |
(w1) = __x.__i.__h; (w0) = __x.__i.__l;}) |
| "dI" ((USItype)(v))); \ |
|
| (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) |
|
| #define __umulsidi3(u, v) \ |
#define __umulsidi3(u, v) \ |
| ({UDItype __w; \ |
({UDItype __w; \ |
| __asm__ ("emul %2,%1,%0" \ |
__asm__ ("emul %2,%1,%0" : "=d" (__w) : "%dI" (u), "dI" (v)); \ |
| : "=d" (__w) \ |
|
| : "%dI" ((USItype)(u)), \ |
|
| "dI" ((USItype)(v))); \ |
|
| __w; }) |
__w; }) |
| #define udiv_qrnnd(q, r, nh, nl, d) \ |
#define udiv_qrnnd(q, r, nh, nl, d) \ |
| do { \ |
do { \ |
| Line 485 extern USItype __udiv_qrnnd (); |
|
| Line 753 extern USItype __udiv_qrnnd (); |
|
| } __nn; \ |
} __nn; \ |
| __nn.__i.__h = (nh); __nn.__i.__l = (nl); \ |
__nn.__i.__h = (nh); __nn.__i.__l = (nl); \ |
| __asm__ ("ediv %d,%n,%0" \ |
__asm__ ("ediv %d,%n,%0" \ |
| : "=d" (__rq.__ll) \ |
: "=d" (__rq.__ll) : "dI" (__nn.__ll), "dI" (d)); \ |
| : "dI" (__nn.__ll), \ |
|
| "dI" ((USItype)(d))); \ |
|
| (r) = __rq.__i.__l; (q) = __rq.__i.__h; \ |
(r) = __rq.__i.__l; (q) = __rq.__i.__h; \ |
| } while (0) |
} while (0) |
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| do { \ |
do { \ |
| USItype __cbtmp; \ |
USItype __cbtmp; \ |
| __asm__ ("scanbit %1,%0" \ |
__asm__ ("scanbit %1,%0" : "=r" (__cbtmp) : "r" (x)); \ |
| : "=r" (__cbtmp) \ |
|
| : "r" ((USItype)(x))); \ |
|
| (count) = __cbtmp ^ 31; \ |
(count) = __cbtmp ^ 31; \ |
| } while (0) |
} while (0) |
| #define COUNT_LEADING_ZEROS_0 (-32) /* sic */ |
#define COUNT_LEADING_ZEROS_0 (-32) /* sic */ |
| Line 506 extern USItype __udiv_qrnnd (); |
|
| Line 770 extern USItype __udiv_qrnnd (); |
|
| struct {USItype __l, __h;} __i; \ |
struct {USItype __l, __h;} __i; \ |
| } __nn; \ |
} __nn; \ |
| __nn.__i.__h = (h); __nn.__i.__l = (l); \ |
__nn.__i.__h = (h); __nn.__i.__l = (l); \ |
| __asm__ ("shre %2,%1,%0" \ |
__asm__ ("shre %2,%1,%0" : "=d" (r) : "dI" (__nn.__ll), "dI" (c)); \ |
| : "=d" (r) : "dI" (__nn.__ll), "dI" (c)); \ |
|
| } |
} |
| #endif /* i960mx */ |
#endif /* i960mx */ |
| #endif /* i960 */ |
#endif /* i960 */ |
| |
|
| #if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32 |
#if (defined (__mc68000__) || defined (__mc68020__) || defined(mc68020) \ |
| |
|| defined (__m68k__) || defined (__mc5200__) || defined (__mc5206e__) \ |
| |
|| defined (__mc5307__)) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("add%.l %5,%1 |
__asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \ |
| addx%.l %3,%0" \ |
: "=d" ((USItype)(sh)), "=&d" ((USItype)(sl)) \ |
| : "=d" ((USItype)(sh)), \ |
: "%0" ((USItype)(ah)), "d" ((USItype)(bh)), \ |
| "=&d" ((USItype)(sl)) \ |
"%1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "%0" ((USItype)(ah)), \ |
|
| "d" ((USItype)(bh)), \ |
|
| "%1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("sub%.l %5,%1 |
__asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \ |
| subx%.l %3,%0" \ |
: "=d" ((USItype)(sh)), "=&d" ((USItype)(sl)) \ |
| : "=d" ((USItype)(sh)), \ |
: "0" ((USItype)(ah)), "d" ((USItype)(bh)), \ |
| "=&d" ((USItype)(sl)) \ |
"1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "0" ((USItype)(ah)), \ |
/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */ |
| "d" ((USItype)(bh)), \ |
#if defined (__mc68020__) || defined(mc68020) \ |
| "1" ((USItype)(al)), \ |
|| defined (__mc68030__) || defined (mc68030) \ |
| "g" ((USItype)(bl))) |
|| defined (__mc68040__) || defined (mc68040) \ |
| #if (defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) |
|| defined (__mcpu32__) || defined (mcpu32) \ |
| |
|| defined (__NeXT__) |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("mulu%.l %3,%1:%0" \ |
__asm__ ("mulu%.l %3,%1:%0" \ |
| : "=d" ((USItype)(w0)), \ |
: "=d" ((USItype)(w0)), "=d" ((USItype)(w1)) \ |
| "=d" ((USItype)(w1)) \ |
: "%0" ((USItype)(u)), "dmi" ((USItype)(v))) |
| : "%0" ((USItype)(u)), \ |
|
| "dmi" ((USItype)(v))) |
|
| #define UMUL_TIME 45 |
#define UMUL_TIME 45 |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| __asm__ ("divu%.l %4,%1:%0" \ |
__asm__ ("divu%.l %4,%1:%0" \ |
| : "=d" ((USItype)(q)), \ |
: "=d" ((USItype)(q)), "=d" ((USItype)(r)) \ |
| "=d" ((USItype)(r)) \ |
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "dmi" ((USItype)(d))) |
| : "0" ((USItype)(n0)), \ |
|
| "1" ((USItype)(n1)), \ |
|
| "dmi" ((USItype)(d))) |
|
| #define UDIV_TIME 90 |
#define UDIV_TIME 90 |
| #define sdiv_qrnnd(q, r, n1, n0, d) \ |
#define sdiv_qrnnd(q, r, n1, n0, d) \ |
| __asm__ ("divs%.l %4,%1:%0" \ |
__asm__ ("divs%.l %4,%1:%0" \ |
| : "=d" ((USItype)(q)), \ |
: "=d" ((USItype)(q)), "=d" ((USItype)(r)) \ |
| "=d" ((USItype)(r)) \ |
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "dmi" ((USItype)(d))) |
| : "0" ((USItype)(n0)), \ |
#else /* for other 68k family members use 16x16->32 multiplication */ |
| "1" ((USItype)(n1)), \ |
|
| "dmi" ((USItype)(d))) |
|
| #define count_leading_zeros(count, x) \ |
|
| __asm__ ("bfffo %1{%b2:%b2},%0" \ |
|
| : "=d" ((USItype)(count)) \ |
|
| : "od" ((USItype)(x)), "n" (0)) |
|
| #define COUNT_LEADING_ZEROS_0 32 |
|
| #else /* not mc68020 */ |
|
| #define umul_ppmm(xh, xl, a, b) \ |
#define umul_ppmm(xh, xl, a, b) \ |
| do { USItype __umul_tmp1, __umul_tmp2; \ |
do { USItype __umul_tmp1, __umul_tmp2; \ |
| __asm__ ("| Inlined umul_ppmm |
__asm__ ("| Inlined umul_ppmm\n" \ |
| move%.l %5,%3 |
" move%.l %5,%3\n" \ |
| move%.l %2,%0 |
" move%.l %2,%0\n" \ |
| move%.w %3,%1 |
" move%.w %3,%1\n" \ |
| swap %3 |
" swap %3\n" \ |
| swap %0 |
" swap %0\n" \ |
| mulu %2,%1 |
" mulu%.w %2,%1\n" \ |
| mulu %3,%0 |
" mulu%.w %3,%0\n" \ |
| mulu %2,%3 |
" mulu%.w %2,%3\n" \ |
| swap %2 |
" swap %2\n" \ |
| mulu %5,%2 |
" mulu%.w %5,%2\n" \ |
| add%.l %3,%2 |
" add%.l %3,%2\n" \ |
| jcc 1f |
" jcc 1f\n" \ |
| add%.l %#0x10000,%0 |
" add%.l %#0x10000,%0\n" \ |
| 1: move%.l %2,%3 |
"1: move%.l %2,%3\n" \ |
| clr%.w %2 |
" clr%.w %2\n" \ |
| swap %2 |
" swap %2\n" \ |
| swap %3 |
" swap %3\n" \ |
| clr%.w %3 |
" clr%.w %3\n" \ |
| add%.l %3,%1 |
" add%.l %3,%1\n" \ |
| addx%.l %2,%0 |
" addx%.l %2,%0\n" \ |
| | End inlined umul_ppmm" \ |
" | End inlined umul_ppmm" \ |
| : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \ |
: "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \ |
| "=d" (__umul_tmp1), "=&d" (__umul_tmp2) \ |
"=d" (__umul_tmp1), "=&d" (__umul_tmp2) \ |
| : "%2" ((USItype)(a)), "d" ((USItype)(b))); \ |
: "%2" ((USItype)(a)), "d" ((USItype)(b))); \ |
| } while (0) |
} while (0) |
| #define UMUL_TIME 100 |
#define UMUL_TIME 100 |
| #define UDIV_TIME 400 |
#define UDIV_TIME 400 |
| #endif /* not mc68020 */ |
#endif /* not mc68020 */ |
| |
/* The '020, '030, '040 and '060 have bitfield insns. */ |
| |
#if defined (__mc68020__) || defined (mc68020) \ |
| |
|| defined (__mc68030__) || defined (mc68030) \ |
| |
|| defined (__mc68040__) || defined (mc68040) \ |
| |
|| defined (__mc68060__) || defined (mc68060) \ |
| |
|| defined (__NeXT__) |
| |
#define count_leading_zeros(count, x) \ |
| |
__asm__ ("bfffo %1{%b2:%b2},%0" \ |
| |
: "=d" ((USItype) (count)) \ |
| |
: "od" ((USItype) (x)), "n" (0)) |
| |
#define COUNT_LEADING_ZEROS_0 32 |
| |
#endif |
| #endif /* mc68000 */ |
#endif /* mc68000 */ |
| |
|
| #if defined (__m88000__) && W_TYPE_SIZE == 32 |
#if defined (__m88000__) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("addu.co %1,%r4,%r5 |
__asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \ |
| addu.ci %0,%r2,%r3" \ |
: "=r" (sh), "=&r" (sl) \ |
| : "=r" ((USItype)(sh)), \ |
: "%rJ" (ah), "rJ" (bh), "%rJ" (al), "rJ" (bl)) |
| "=&r" ((USItype)(sl)) \ |
|
| : "%rJ" ((USItype)(ah)), \ |
|
| "rJ" ((USItype)(bh)), \ |
|
| "%rJ" ((USItype)(al)), \ |
|
| "rJ" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("subu.co %1,%r4,%r5 |
__asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \ |
| subu.ci %0,%r2,%r3" \ |
: "=r" (sh), "=&r" (sl) \ |
| : "=r" ((USItype)(sh)), \ |
: "rJ" (ah), "rJ" (bh), "rJ" (al), "rJ" (bl)) |
| "=&r" ((USItype)(sl)) \ |
|
| : "rJ" ((USItype)(ah)), \ |
|
| "rJ" ((USItype)(bh)), \ |
|
| "rJ" ((USItype)(al)), \ |
|
| "rJ" ((USItype)(bl))) |
|
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| do { \ |
do { \ |
| USItype __cbtmp; \ |
USItype __cbtmp; \ |
| __asm__ ("ff1 %0,%1" \ |
__asm__ ("ff1 %0,%1" : "=r" (__cbtmp) : "r" (x)); \ |
| : "=r" (__cbtmp) \ |
|
| : "r" ((USItype)(x))); \ |
|
| (count) = __cbtmp ^ 31; \ |
(count) = __cbtmp ^ 31; \ |
| } while (0) |
} while (0) |
| #define COUNT_LEADING_ZEROS_0 63 /* sic */ |
#define COUNT_LEADING_ZEROS_0 63 /* sic */ |
| Line 626 extern USItype __udiv_qrnnd (); |
|
| Line 875 extern USItype __udiv_qrnnd (); |
|
| do { \ |
do { \ |
| union {UDItype __ll; \ |
union {UDItype __ll; \ |
| struct {USItype __h, __l;} __i; \ |
struct {USItype __h, __l;} __i; \ |
| } __xx; \ |
} __x; \ |
| __asm__ ("mulu.d %0,%1,%2" \ |
__asm__ ("mulu.d %0,%1,%2" : "=r" (__x.__ll) : "r" (u), "r" (v)); \ |
| : "=r" (__xx.__ll) \ |
(wh) = __x.__i.__h; \ |
| : "r" ((USItype)(u)), \ |
(wl) = __x.__i.__l; \ |
| "r" ((USItype)(v))); \ |
|
| (wh) = __xx.__i.__h; \ |
|
| (wl) = __xx.__i.__l; \ |
|
| } while (0) |
} while (0) |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| ({union {UDItype __ll; \ |
({union {UDItype __ll; \ |
| struct {USItype __h, __l;} __i; \ |
struct {USItype __h, __l;} __i; \ |
| } __xx; \ |
} __x, __q; \ |
| USItype __q; \ |
__x.__i.__h = (n1); __x.__i.__l = (n0); \ |
| __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ |
|
| __asm__ ("divu.d %0,%1,%2" \ |
__asm__ ("divu.d %0,%1,%2" \ |
| : "=r" (__q) \ |
: "=r" (__q.__ll) : "r" (__x.__ll), "r" (d)); \ |
| : "r" (__xx.__ll), \ |
(r) = (n0) - __q.__l * (d); (q) = __q.__l; }) |
| "r" ((USItype)(d))); \ |
|
| (r) = (n0) - __q * (d); (q) = __q; }) |
|
| #define UMUL_TIME 5 |
#define UMUL_TIME 5 |
| #define UDIV_TIME 25 |
#define UDIV_TIME 25 |
| #else |
#else |
| Line 653 extern USItype __udiv_qrnnd (); |
|
| Line 896 extern USItype __udiv_qrnnd (); |
|
| #endif /* __m88110__ */ |
#endif /* __m88110__ */ |
| #endif /* __m88000__ */ |
#endif /* __m88000__ */ |
| |
|
| #if defined (__mips__) && W_TYPE_SIZE == 32 |
#if defined (__mips) && W_TYPE_SIZE == 32 |
| #if __GNUC__ > 2 || __GNUC_MINOR__ >= 7 |
#if __GNUC__ > 2 || __GNUC_MINOR__ >= 7 |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("multu %2,%3" \ |
__asm__ ("multu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v)) |
| : "=l" ((USItype)(w0)), \ |
|
| "=h" ((USItype)(w1)) \ |
|
| : "d" ((USItype)(u)), \ |
|
| "d" ((USItype)(v))) |
|
| #else |
#else |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("multu %2,%3 |
__asm__ ("multu %2,%3\n\tmflo %0\n\tmfhi %1" \ |
| mflo %0 |
: "=d" (w0), "=d" (w1) : "d" (u), "d" (v)) |
| mfhi %1" \ |
|
| : "=d" ((USItype)(w0)), \ |
|
| "=d" ((USItype)(w1)) \ |
|
| : "d" ((USItype)(u)), \ |
|
| "d" ((USItype)(v))) |
|
| #endif |
#endif |
| #define UMUL_TIME 10 |
#define UMUL_TIME 10 |
| #define UDIV_TIME 100 |
#define UDIV_TIME 100 |
| #endif /* __mips__ */ |
#endif /* __mips */ |
| |
|
| #if (defined (__mips) && __mips >= 3) && W_TYPE_SIZE == 64 |
#if (defined (__mips) && __mips >= 3) && W_TYPE_SIZE == 64 |
| #if __GNUC__ > 2 || __GNUC_MINOR__ >= 7 |
#if __GNUC__ > 2 || __GNUC_MINOR__ >= 7 |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("dmultu %2,%3" \ |
__asm__ ("dmultu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v)) |
| : "=l" ((UDItype)(w0)), \ |
|
| "=h" ((UDItype)(w1)) \ |
|
| : "d" ((UDItype)(u)), \ |
|
| "d" ((UDItype)(v))) |
|
| #else |
#else |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("dmultu %2,%3 |
__asm__ ("dmultu %2,%3\n\tmflo %0\n\tmfhi %1" \ |
| mflo %0 |
: "=d" (w0), "=d" (w1) : "d" (u), "d" (v)) |
| mfhi %1" \ |
|
| : "=d" ((UDItype)(w0)), \ |
|
| "=d" ((UDItype)(w1)) \ |
|
| : "d" ((UDItype)(u)), \ |
|
| "d" ((UDItype)(v))) |
|
| #endif |
#endif |
| #define UMUL_TIME 20 |
#define UMUL_TIME 20 |
| #define UDIV_TIME 140 |
#define UDIV_TIME 140 |
| #endif /* __mips__ */ |
#endif /* __mips */ |
| |
|
| #if defined (__ns32000__) && W_TYPE_SIZE == 32 |
#if defined (__ns32000__) && W_TYPE_SIZE == 32 |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| ({union {UDItype __ll; \ |
({union {UDItype __ll; \ |
| struct {USItype __l, __h;} __i; \ |
struct {USItype __l, __h;} __i; \ |
| } __xx; \ |
} __x; \ |
| __asm__ ("meid %2,%0" \ |
__asm__ ("meid %2,%0" \ |
| : "=g" (__xx.__ll) \ |
: "=g" (__x.__ll) \ |
| : "%0" ((USItype)(u)), \ |
: "%0" ((USItype)(u)), "g" ((USItype)(v))); \ |
| "g" ((USItype)(v))); \ |
(w1) = __x.__i.__h; (w0) = __x.__i.__l;}) |
| (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) |
|
| #define __umulsidi3(u, v) \ |
#define __umulsidi3(u, v) \ |
| ({UDItype __w; \ |
({UDItype __w; \ |
| __asm__ ("meid %2,%0" \ |
__asm__ ("meid %2,%0" \ |
| : "=g" (__w) \ |
: "=g" (__w) \ |
| : "%0" ((USItype)(u)), \ |
: "%0" ((USItype)(u)), "g" ((USItype)(v))); \ |
| "g" ((USItype)(v))); \ |
|
| __w; }) |
__w; }) |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| ({union {UDItype __ll; \ |
({union {UDItype __ll; \ |
| struct {USItype __l, __h;} __i; \ |
struct {USItype __l, __h;} __i; \ |
| } __xx; \ |
} __x; \ |
| __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ |
__x.__i.__h = (n1); __x.__i.__l = (n0); \ |
| __asm__ ("deid %2,%0" \ |
__asm__ ("deid %2,%0" \ |
| : "=g" (__xx.__ll) \ |
: "=g" (__x.__ll) \ |
| : "0" (__xx.__ll), \ |
: "0" (__x.__ll), "g" ((USItype)(d))); \ |
| "g" ((USItype)(d))); \ |
(r) = __x.__i.__l; (q) = __x.__i.__h; }) |
| (r) = __xx.__i.__l; (q) = __xx.__i.__h; }) |
|
| #define count_trailing_zeros(count,x) \ |
#define count_trailing_zeros(count,x) \ |
| do { |
do { \ |
| __asm__ ("ffsd %2,%0" \ |
__asm__ ("ffsd %2,%0" \ |
| : "=r" ((USItype) (count)) \ |
: "=r" ((USItype) (count)) \ |
| : "0" ((USItype) 0), \ |
: "0" ((USItype) 0), "r" ((USItype) (x))); \ |
| "r" ((USItype) (x))); \ |
|
| } while (0) |
} while (0) |
| #endif /* __ns32000__ */ |
#endif /* __ns32000__ */ |
| |
|
| #if (defined (_ARCH_PPC) || defined (_IBMR2)) && W_TYPE_SIZE == 32 |
/* FIXME: We should test _IBMR2 here when we add assembly support for the |
| |
system vendor compilers. |
| |
FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good |
| |
enough, since that hits ARM and m68k too. */ |
| |
#if (defined (_ARCH_PPC) /* AIX */ \ |
| |
|| defined (_ARCH_PWR) /* AIX */ \ |
| |
|| defined (__powerpc__) /* gcc */ \ |
| |
|| defined (__POWERPC__) /* BEOS */ \ |
| |
|| defined (__ppc__) /* Darwin */ \ |
| |
|| defined (PPC) /* GNU/Linux, SysV */ \ |
| |
) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| do { \ |
do { \ |
| if (__builtin_constant_p (bh) && (bh) == 0) \ |
if (__builtin_constant_p (bh) && (bh) == 0) \ |
| __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ |
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ |
| "=&r" ((USItype)(sl)) \ |
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ |
| : "%r" ((USItype)(ah)), \ |
|
| "%r" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl))); \ |
|
| else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \ |
|
| __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ |
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ |
| "=&r" ((USItype)(sl)) \ |
|
| : "%r" ((USItype)(ah)), \ |
|
| "%r" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl))); \ |
|
| else \ |
else \ |
| __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ |
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) \ |
| "=&r" ((USItype)(sl)) \ |
: "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ |
| : "%r" ((USItype)(ah)), \ |
|
| "r" ((USItype)(bh)), \ |
|
| "%r" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl))); \ |
|
| } while (0) |
} while (0) |
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| do { \ |
do { \ |
| if (__builtin_constant_p (ah) && (ah) == 0) \ |
if (__builtin_constant_p (ah) && (ah) == 0) \ |
| __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ |
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ |
| "=&r" ((USItype)(sl)) \ |
else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \ |
| : "r" ((USItype)(bh)), \ |
|
| "rI" ((USItype)(al)), \ |
|
| "r" ((USItype)(bl))); \ |
|
| else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \ |
|
| __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ |
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ |
| "=&r" ((USItype)(sl)) \ |
|
| : "r" ((USItype)(bh)), \ |
|
| "rI" ((USItype)(al)), \ |
|
| "r" ((USItype)(bl))); \ |
|
| else if (__builtin_constant_p (bh) && (bh) == 0) \ |
else if (__builtin_constant_p (bh) && (bh) == 0) \ |
| __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ |
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ |
| "=&r" ((USItype)(sl)) \ |
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ |
| : "r" ((USItype)(ah)), \ |
|
| "rI" ((USItype)(al)), \ |
|
| "r" ((USItype)(bl))); \ |
|
| else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \ |
|
| __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ |
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ |
| "=&r" ((USItype)(sl)) \ |
|
| : "r" ((USItype)(ah)), \ |
|
| "rI" ((USItype)(al)), \ |
|
| "r" ((USItype)(bl))); \ |
|
| else \ |
else \ |
| __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ |
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ |
| : "=r" ((USItype)(sh)), \ |
: "=r" (sh), "=&r" (sl) \ |
| "=&r" ((USItype)(sl)) \ |
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ |
| : "r" ((USItype)(ah)), \ |
|
| "r" ((USItype)(bh)), \ |
|
| "rI" ((USItype)(al)), \ |
|
| "r" ((USItype)(bl))); \ |
|
| } while (0) |
} while (0) |
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| __asm__ ("{cntlz|cntlzw} %0,%1" \ |
__asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x)) |
| : "=r" ((USItype)(count)) \ |
|
| : "r" ((USItype)(x))) |
|
| #define COUNT_LEADING_ZEROS_0 32 |
#define COUNT_LEADING_ZEROS_0 32 |
| #if defined (_ARCH_PPC) |
#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \ |
| |
|| defined (__ppc__) || defined (PPC) || defined (__vxworks__) |
| #define umul_ppmm(ph, pl, m0, m1) \ |
#define umul_ppmm(ph, pl, m0, m1) \ |
| do { \ |
do { \ |
| USItype __m0 = (m0), __m1 = (m1); \ |
USItype __m0 = (m0), __m1 = (m1); \ |
| __asm__ ("mulhwu %0,%1,%2" \ |
__asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ |
| : "=r" ((USItype) ph) \ |
|
| : "%r" (__m0), \ |
|
| "r" (__m1)); \ |
|
| (pl) = __m0 * __m1; \ |
(pl) = __m0 * __m1; \ |
| } while (0) |
} while (0) |
| #define UMUL_TIME 15 |
#define UMUL_TIME 15 |
| #define smul_ppmm(ph, pl, m0, m1) \ |
#define smul_ppmm(ph, pl, m0, m1) \ |
| do { \ |
do { \ |
| SItype __m0 = (m0), __m1 = (m1); \ |
SItype __m0 = (m0), __m1 = (m1); \ |
| __asm__ ("mulhw %0,%1,%2" \ |
__asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ |
| : "=r" ((SItype) ph) \ |
|
| : "%r" (__m0), \ |
|
| "r" (__m1)); \ |
|
| (pl) = __m0 * __m1; \ |
(pl) = __m0 * __m1; \ |
| } while (0) |
} while (0) |
| #define SMUL_TIME 14 |
#define SMUL_TIME 14 |
| #define UDIV_TIME 120 |
#define UDIV_TIME 120 |
| #else |
#else |
| #define umul_ppmm(xh, xl, m0, m1) \ |
|
| do { \ |
|
| USItype __m0 = (m0), __m1 = (m1); \ |
|
| __asm__ ("mul %0,%2,%3" \ |
|
| : "=r" ((USItype)(xh)), \ |
|
| "=q" ((USItype)(xl)) \ |
|
| : "r" (__m0), \ |
|
| "r" (__m1)); \ |
|
| (xh) += ((((SItype) __m0 >> 31) & __m1) \ |
|
| + (((SItype) __m1 >> 31) & __m0)); \ |
|
| } while (0) |
|
| #define UMUL_TIME 8 |
#define UMUL_TIME 8 |
| #define smul_ppmm(xh, xl, m0, m1) \ |
#define smul_ppmm(xh, xl, m0, m1) \ |
| __asm__ ("mul %0,%2,%3" \ |
__asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1)) |
| : "=r" ((SItype)(xh)), \ |
|
| "=q" ((SItype)(xl)) \ |
|
| : "r" (m0), \ |
|
| "r" (m1)) |
|
| #define SMUL_TIME 4 |
#define SMUL_TIME 4 |
| #define sdiv_qrnnd(q, r, nh, nl, d) \ |
#define sdiv_qrnnd(q, r, nh, nl, d) \ |
| __asm__ ("div %0,%2,%4" \ |
__asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d)) |
| : "=r" ((SItype)(q)), "=q" ((SItype)(r)) \ |
|
| : "r" ((SItype)(nh)), "1" ((SItype)(nl)), "r" ((SItype)(d))) |
|
| #define UDIV_TIME 100 |
#define UDIV_TIME 100 |
| #endif |
#endif |
| #endif /* Power architecture variants. */ |
#endif /* 32-bit POWER architecture variants. */ |
| |
|
| |
/* We should test _IBMR2 here when we add assembly support for the system |
| |
vendor compilers. */ |
| |
#if (defined (_ARCH_PPC) || defined (__powerpc__)) && W_TYPE_SIZE == 64 |
| |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| |
do { \ |
| |
if (__builtin_constant_p (bh) && (bh) == 0) \ |
| |
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ |
| |
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ |
| |
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ |
| |
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ |
| |
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ |
| |
else \ |
| |
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ |
| |
} while (0) |
| |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| |
do { \ |
| |
if (__builtin_constant_p (ah) && (ah) == 0) \ |
| |
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ |
| |
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ |
| |
else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \ |
| |
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ |
| |
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ |
| |
else if (__builtin_constant_p (bh) && (bh) == 0) \ |
| |
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ |
| |
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ |
| |
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ |
| |
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ |
| |
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ |
| |
else \ |
| |
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ |
| |
} while (0) |
| |
#define count_leading_zeros(count, x) \ |
| |
__asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x)) |
| |
#define COUNT_LEADING_ZEROS_0 64 |
| |
#define umul_ppmm(ph, pl, m0, m1) \ |
| |
do { \ |
| |
UDItype __m0 = (m0), __m1 = (m1); \ |
| |
__asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ |
| |
(pl) = __m0 * __m1; \ |
| |
} while (0) |
| |
#define UMUL_TIME 15 |
| |
#define smul_ppmm(ph, pl, m0, m1) \ |
| |
do { \ |
| |
DItype __m0 = (m0), __m1 = (m1); \ |
| |
__asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ |
| |
(pl) = __m0 * __m1; \ |
| |
} while (0) |
| |
#define SMUL_TIME 14 /* ??? */ |
| |
#define UDIV_TIME 120 /* ??? */ |
| |
#endif /* 64-bit PowerPC. */ |
| |
|
| #if defined (__pyr__) && W_TYPE_SIZE == 32 |
#if defined (__pyr__) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("addw %5,%1 |
__asm__ ("addw %5,%1\n\taddwc %3,%0" \ |
| addwc %3,%0" \ |
: "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \ |
| : "=r" ((USItype)(sh)), \ |
: "%0" ((USItype)(ah)), "g" ((USItype)(bh)), \ |
| "=&r" ((USItype)(sl)) \ |
"%1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "%0" ((USItype)(ah)), \ |
|
| "g" ((USItype)(bh)), \ |
|
| "%1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("subw %5,%1 |
__asm__ ("subw %5,%1\n\tsubwb %3,%0" \ |
| subwb %3,%0" \ |
: "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \ |
| : "=r" ((USItype)(sh)), \ |
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \ |
| "=&r" ((USItype)(sl)) \ |
"1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "0" ((USItype)(ah)), \ |
|
| "g" ((USItype)(bh)), \ |
|
| "1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */ |
/* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */ |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| ({union {UDItype __ll; \ |
({union {UDItype __ll; \ |
| struct {USItype __h, __l;} __i; \ |
struct {USItype __h, __l;} __i; \ |
| } __xx; \ |
} __x; \ |
| __asm__ ("movw %1,%R0 |
__asm__ ("movw %1,%R0\n\tuemul %2,%0" \ |
| uemul %2,%0" \ |
: "=&r" (__x.__ll) \ |
| : "=&r" (__xx.__ll) \ |
: "g" ((USItype) (u)), "g" ((USItype)(v))); \ |
| : "g" ((USItype) (u)), \ |
(w1) = __x.__i.__h; (w0) = __x.__i.__l;}) |
| "g" ((USItype)(v))); \ |
|
| (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) |
|
| #endif /* __pyr__ */ |
#endif /* __pyr__ */ |
| |
|
| #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 |
#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("a %1,%5 |
__asm__ ("a %1,%5\n\tae %0,%3" \ |
| ae %0,%3" \ |
: "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \ |
| : "=r" ((USItype)(sh)), \ |
: "%0" ((USItype)(ah)), "r" ((USItype)(bh)), \ |
| "=&r" ((USItype)(sl)) \ |
"%1" ((USItype)(al)), "r" ((USItype)(bl))) |
| : "%0" ((USItype)(ah)), \ |
|
| "r" ((USItype)(bh)), \ |
|
| "%1" ((USItype)(al)), \ |
|
| "r" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("s %1,%5 |
__asm__ ("s %1,%5\n\tse %0,%3" \ |
| se %0,%3" \ |
: "=r" ((USItype)(sh)), "=&r" ((USItype)(sl)) \ |
| : "=r" ((USItype)(sh)), \ |
: "0" ((USItype)(ah)), "r" ((USItype)(bh)), \ |
| "=&r" ((USItype)(sl)) \ |
"1" ((USItype)(al)), "r" ((USItype)(bl))) |
| : "0" ((USItype)(ah)), \ |
#define smul_ppmm(ph, pl, m0, m1) \ |
| "r" ((USItype)(bh)), \ |
__asm__ ( \ |
| "1" ((USItype)(al)), \ |
"s r2,r2\n" \ |
| "r" ((USItype)(bl))) |
" mts r10,%2\n" \ |
| #define umul_ppmm(ph, pl, m0, m1) \ |
" m r2,%3\n" \ |
| do { \ |
" m r2,%3\n" \ |
| USItype __m0 = (m0), __m1 = (m1); \ |
" m r2,%3\n" \ |
| __asm__ ( \ |
" m r2,%3\n" \ |
| "s r2,r2 |
" m r2,%3\n" \ |
| mts r10,%2 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" m r2,%3\n" \ |
| m r2,%3 |
" cas %0,r2,r0\n" \ |
| m r2,%3 |
" mfs r10,%1" \ |
| m r2,%3 |
: "=r" ((USItype)(ph)), "=r" ((USItype)(pl)) \ |
| m r2,%3 |
: "%r" ((USItype)(m0)), "r" ((USItype)(m1)) \ |
| m r2,%3 |
: "r2") |
| m r2,%3 |
|
| cas %0,r2,r0 |
|
| mfs r10,%1" \ |
|
| : "=r" ((USItype)(ph)), \ |
|
| "=r" ((USItype)(pl)) \ |
|
| : "%r" (__m0), \ |
|
| "r" (__m1) \ |
|
| : "r2"); \ |
|
| (ph) += ((((SItype) __m0 >> 31) & __m1) \ |
|
| + (((SItype) __m1 >> 31) & __m0)); \ |
|
| } while (0) |
|
| #define UMUL_TIME 20 |
#define UMUL_TIME 20 |
| #define UDIV_TIME 200 |
#define UDIV_TIME 200 |
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| do { \ |
do { \ |
| if ((x) >= 0x10000) \ |
if ((x) >= 0x10000) \ |
| __asm__ ("clz %0,%1" \ |
__asm__ ("clz %0,%1" \ |
| : "=r" ((USItype)(count)) \ |
: "=r" ((USItype)(count)) : "r" ((USItype)(x) >> 16)); \ |
| : "r" ((USItype)(x) >> 16)); \ |
|
| else \ |
else \ |
| { \ |
{ \ |
| __asm__ ("clz %0,%1" \ |
__asm__ ("clz %0,%1" \ |
| : "=r" ((USItype)(count)) \ |
: "=r" ((USItype)(count)) : "r" ((USItype)(x))); \ |
| : "r" ((USItype)(x))); \ |
|
| (count) += 16; \ |
(count) += 16; \ |
| } \ |
} \ |
| } while (0) |
} while (0) |
| Line 956 extern USItype __udiv_qrnnd (); |
|
| Line 1159 extern USItype __udiv_qrnnd (); |
|
| |
|
| #if defined (__sh2__) && W_TYPE_SIZE == 32 |
#if defined (__sh2__) && W_TYPE_SIZE == 32 |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ( \ |
__asm__ ("dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \ |
| "dmulu.l %2,%3 |
: "=r" (w1), "=r" (w0) : "r" (u), "r" (v) : "macl", "mach") |
| sts macl,%1 |
|
| sts mach,%0" \ |
|
| : "=r" ((USItype)(w1)), \ |
|
| "=r" ((USItype)(w0)) \ |
|
| : "r" ((USItype)(u)), \ |
|
| "r" ((USItype)(v)) \ |
|
| : "macl", "mach") |
|
| #define UMUL_TIME 5 |
#define UMUL_TIME 5 |
| #endif |
#endif |
| |
|
| #if defined (__sparc__) && W_TYPE_SIZE == 32 |
#if defined (__sparc__) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("addcc %r4,%5,%1 |
__asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \ |
| addx %r2,%3,%0" \ |
: "=r" (sh), "=&r" (sl) \ |
| : "=r" ((USItype)(sh)), \ |
: "%rJ" (ah), "rI" (bh),"%rJ" (al), "rI" (bl) \ |
| "=&r" ((USItype)(sl)) \ |
|
| : "%rJ" ((USItype)(ah)), \ |
|
| "rI" ((USItype)(bh)), \ |
|
| "%rJ" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl)) \ |
|
| __CLOBBER_CC) |
__CLOBBER_CC) |
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("subcc %r4,%5,%1 |
__asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \ |
| subx %r2,%3,%0" \ |
: "=r" (sh), "=&r" (sl) \ |
| : "=r" ((USItype)(sh)), \ |
: "rJ" (ah), "rI" (bh), "rJ" (al), "rI" (bl) \ |
| "=&r" ((USItype)(sl)) \ |
|
| : "rJ" ((USItype)(ah)), \ |
|
| "rI" ((USItype)(bh)), \ |
|
| "rJ" ((USItype)(al)), \ |
|
| "rI" ((USItype)(bl)) \ |
|
| __CLOBBER_CC) |
__CLOBBER_CC) |
| #if defined (__sparc_v8__) |
/* FIXME: When gcc -mcpu=v9 is used on solaris, gcc/config/sol2-sld-64.h |
| |
doesn't define anything to indicate that to us, it only sets __sparcv8. */ |
| |
#if defined (__sparc_v9__) || defined (__sparcv9) |
| |
/* Perhaps we should use floating-point operations here? */ |
| |
#if 0 |
| |
/* Triggers a bug making mpz/tests/t-gcd.c fail. |
| |
Perhaps we simply need explicitly zero-extend the inputs? */ |
| |
#define umul_ppmm(w1, w0, u, v) \ |
| |
__asm__ ("mulx %2,%3,%%g1; srl %%g1,0,%1; srlx %%g1,32,%0" : \ |
| |
"=r" (w1), "=r" (w0) : "r" (u), "r" (v) : "g1") |
| |
#else |
| |
/* Use v8 umul until above bug is fixed. */ |
| |
#define umul_ppmm(w1, w0, u, v) \ |
| |
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v)) |
| |
#endif |
| |
/* Use a plain v8 divide for v9. */ |
| |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| |
do { \ |
| |
USItype __q; \ |
| |
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \ |
| |
: "=r" (__q) : "r" (n1), "r" (n0), "r" (d)); \ |
| |
(r) = (n0) - __q * (d); \ |
| |
(q) = __q; \ |
| |
} while (0) |
| |
#else |
| |
#if defined (__sparc_v8__) /* gcc normal */ \ |
| |
|| defined (__sparcv8) /* gcc solaris */ |
| /* Don't match immediate range because, 1) it is not often useful, |
/* Don't match immediate range because, 1) it is not often useful, |
| 2) the 'I' flag thinks of the range as a 13 bit signed interval, |
2) the 'I' flag thinks of the range as a 13 bit signed interval, |
| while we want to match a 13 bit interval, sign extended to 32 bits, |
while we want to match a 13 bit interval, sign extended to 32 bits, |
| but INTERPRETED AS UNSIGNED. */ |
but INTERPRETED AS UNSIGNED. */ |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("umul %2,%3,%1;rd %%y,%0" \ |
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v)) |
| : "=r" ((USItype)(w1)), \ |
|
| "=r" ((USItype)(w0)) \ |
|
| : "r" ((USItype)(u)), \ |
|
| "r" ((USItype)(v))) |
|
| #define UMUL_TIME 5 |
#define UMUL_TIME 5 |
| #ifndef SUPERSPARC /* SuperSPARC's udiv only handles 53 bit dividends */ |
|
| |
#if HAVE_HOST_CPU_supersparc |
| |
#define UDIV_TIME 60 /* SuperSPARC timing */ |
| |
#else |
| |
/* Don't use this on SuperSPARC because its udiv only handles 53 bit |
| |
dividends and will trap to the kernel for the rest. */ |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| do { \ |
do { \ |
| USItype __q; \ |
USItype __q; \ |
| __asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \ |
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \ |
| : "=r" ((USItype)(__q)) \ |
: "=r" (__q) : "r" (n1), "r" (n0), "r" (d)); \ |
| : "r" ((USItype)(n1)), \ |
|
| "r" ((USItype)(n0)), \ |
|
| "r" ((USItype)(d))); \ |
|
| (r) = (n0) - __q * (d); \ |
(r) = (n0) - __q * (d); \ |
| (q) = __q; \ |
(q) = __q; \ |
| } while (0) |
} while (0) |
| #define UDIV_TIME 25 |
#define UDIV_TIME 25 |
| #endif /* SUPERSPARC */ |
#endif /* HAVE_HOST_CPU_supersparc */ |
| |
|
| #else /* ! __sparc_v8__ */ |
#else /* ! __sparc_v8__ */ |
| #if defined (__sparclite__) |
#if defined (__sparclite__) |
| /* This has hardware multiply but not divide. It also has two additional |
/* This has hardware multiply but not divide. It also has two additional |
| instructions scan (ffs from high bit) and divscc. */ |
instructions scan (ffs from high bit) and divscc. */ |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("umul %2,%3,%1;rd %%y,%0" \ |
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v)) |
| : "=r" ((USItype)(w1)), \ |
|
| "=r" ((USItype)(w0)) \ |
|
| : "r" ((USItype)(u)), \ |
|
| "r" ((USItype)(v))) |
|
| #define UMUL_TIME 5 |
#define UMUL_TIME 5 |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| __asm__ ("! Inlined udiv_qrnnd |
__asm__ ("! Inlined udiv_qrnnd\n" \ |
| wr %%g0,%2,%%y ! Not a delayed write for sparclite |
" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \ |
| tst %%g0 |
" tst %%g0\n" \ |
| divscc %3,%4,%%g1 |
" divscc %3,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%%g1 |
" divscc %%g1,%4,%%g1\n" \ |
| divscc %%g1,%4,%0 |
" divscc %%g1,%4,%0\n" \ |
| rd %%y,%1 |
" rd %%y,%1\n" \ |
| bl,a 1f |
" bl,a 1f\n" \ |
| add %1,%4,%1 |
" add %1,%4,%1\n" \ |
| 1: ! End of inline udiv_qrnnd" \ |
"1: ! End of inline udiv_qrnnd" \ |
| : "=r" ((USItype)(q)), \ |
: "=r" (q), "=r" (r) : "r" (n1), "r" (n0), "rI" (d) \ |
| "=r" ((USItype)(r)) \ |
|
| : "r" ((USItype)(n1)), \ |
|
| "r" ((USItype)(n0)), \ |
|
| "rI" ((USItype)(d)) \ |
|
| : "%g1" __AND_CLOBBER_CC) |
: "%g1" __AND_CLOBBER_CC) |
| #define UDIV_TIME 37 |
#define UDIV_TIME 37 |
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| __asm__ ("scan %1,0,%0" \ |
__asm__ ("scan %1,1,%0" : "=r" (count) : "r" (x)) |
| : "=r" ((USItype)(x)) \ |
|
| : "r" ((USItype)(count))) |
|
| /* Early sparclites return 63 for an argument of 0, but they warn that future |
/* Early sparclites return 63 for an argument of 0, but they warn that future |
| implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0 |
implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0 |
| undefined. */ |
undefined. */ |
| #endif /* __sparclite__ */ |
#endif /* __sparclite__ */ |
| #endif /* __sparc_v8__ */ |
#endif /* __sparc_v8__ */ |
| |
#endif /* __sparc_v9__ */ |
| /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */ |
/* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */ |
| #ifndef umul_ppmm |
#ifndef umul_ppmm |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| __asm__ ("! Inlined umul_ppmm |
__asm__ ("! Inlined umul_ppmm\n" \ |
| wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr |
" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \ |
| sra %3,31,%%g2 ! Don't move this insn |
" sra %3,31,%%g2 ! Don't move this insn\n" \ |
| and %2,%%g2,%%g2 ! Don't move this insn |
" and %2,%%g2,%%g2 ! Don't move this insn\n" \ |
| andcc %%g0,0,%%g1 ! Don't move this insn |
" andcc %%g0,0,%%g1 ! Don't move this insn\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,%3,%%g1 |
" mulscc %%g1,%3,%%g1\n" \ |
| mulscc %%g1,0,%%g1 |
" mulscc %%g1,0,%%g1\n" \ |
| add %%g1,%%g2,%0 |
" add %%g1,%%g2,%0\n" \ |
| rd %%y,%1" \ |
" rd %%y,%1" \ |
| : "=r" ((USItype)(w1)), \ |
: "=r" (w1), "=r" (w0) : "%rI" (u), "r" (v) \ |
| "=r" ((USItype)(w0)) \ |
|
| : "%rI" ((USItype)(u)), \ |
|
| "r" ((USItype)(v)) \ |
|
| : "%g1", "%g2" __AND_CLOBBER_CC) |
: "%g1", "%g2" __AND_CLOBBER_CC) |
| #define UMUL_TIME 39 /* 39 instructions */ |
#define UMUL_TIME 39 /* 39 instructions */ |
| #endif |
#endif |
| #ifndef udiv_qrnnd |
#ifndef udiv_qrnnd |
| #ifndef LONGLONG_STANDALONE |
#ifndef LONGLONG_STANDALONE |
| #define udiv_qrnnd(q, r, n1, n0, d) \ |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| do { USItype __r; \ |
do { UWtype __r; \ |
| (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ |
(q) = __MPN(udiv_qrnnd) (&__r, (n1), (n0), (d)); \ |
| (r) = __r; \ |
(r) = __r; \ |
| } while (0) |
} while (0) |
| extern USItype __udiv_qrnnd (); |
extern UWtype __MPN(udiv_qrnnd) _PROTO ((UWtype *, UWtype, UWtype, UWtype)); |
| |
#ifndef UDIV_TIME |
| #define UDIV_TIME 140 |
#define UDIV_TIME 140 |
| |
#endif |
| #endif /* LONGLONG_STANDALONE */ |
#endif /* LONGLONG_STANDALONE */ |
| #endif /* udiv_qrnnd */ |
#endif /* udiv_qrnnd */ |
| #endif /* __sparc__ */ |
#endif /* __sparc__ */ |
| |
|
| |
#if defined (__sparc__) && W_TYPE_SIZE == 64 |
| |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ( \ |
| |
"addcc %r4,%5,%1\n" \ |
| |
" addccc %r6,%7,%%g0\n" \ |
| |
" addc %r2,%3,%0" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "%rJ" (ah), "rI" (bh), "%rJ" (al), "rI" (bl), \ |
| |
"%rJ" ((al) >> 32), "rI" ((bl) >> 32) \ |
| |
__CLOBBER_CC) |
| |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| |
__asm__ ( \ |
| |
"subcc %r4,%5,%1\n" \ |
| |
" subccc %r6,%7,%%g0\n" \ |
| |
" subc %r2,%3,%0" \ |
| |
: "=r" (sh), "=&r" (sl) \ |
| |
: "rJ" (ah), "rI" (bh), "rJ" (al), "rI" (bl), \ |
| |
"rJ" ((al) >> 32), "rI" ((bl) >> 32) \ |
| |
__CLOBBER_CC) |
| |
#endif |
| |
|
| #if defined (__vax__) && W_TYPE_SIZE == 32 |
#if defined (__vax__) && W_TYPE_SIZE == 32 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("addl2 %5,%1 |
__asm__ ("addl2 %5,%1\n\tadwc %3,%0" \ |
| adwc %3,%0" \ |
: "=g" ((USItype)(sh)), "=&g" ((USItype)(sl)) \ |
| : "=g" ((USItype)(sh)), \ |
: "%0" ((USItype)(ah)), "g" ((USItype)(bh)), \ |
| "=&g" ((USItype)(sl)) \ |
"%1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "%0" ((USItype)(ah)), \ |
|
| "g" ((USItype)(bh)), \ |
|
| "%1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("subl2 %5,%1 |
__asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \ |
| sbwc %3,%0" \ |
: "=g" ((USItype)(sh)), "=&g" ((USItype)(sl)) \ |
| : "=g" ((USItype)(sh)), \ |
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \ |
| "=&g" ((USItype)(sl)) \ |
"1" ((USItype)(al)), "g" ((USItype)(bl))) |
| : "0" ((USItype)(ah)), \ |
#define smul_ppmm(xh, xl, m0, m1) \ |
| "g" ((USItype)(bh)), \ |
|
| "1" ((USItype)(al)), \ |
|
| "g" ((USItype)(bl))) |
|
| #define umul_ppmm(xh, xl, m0, m1) \ |
|
| do { \ |
do { \ |
| union {UDItype __ll; \ |
union {UDItype __ll; \ |
| struct {USItype __l, __h;} __i; \ |
struct {USItype __l, __h;} __i; \ |
| } __xx; \ |
} __x; \ |
| USItype __m0 = (m0), __m1 = (m1); \ |
USItype __m0 = (m0), __m1 = (m1); \ |
| __asm__ ("emul %1,%2,$0,%0" \ |
__asm__ ("emul %1,%2,$0,%0" \ |
| : "=g" (__xx.__ll) \ |
: "=g" (__x.__ll) : "g" (__m0), "g" (__m1)); \ |
| : "g" (__m0), \ |
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \ |
| "g" (__m1)); \ |
|
| (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ |
|
| (xh) += ((((SItype) __m0 >> 31) & __m1) \ |
|
| + (((SItype) __m1 >> 31) & __m0)); \ |
|
| } while (0) |
} while (0) |
| #define sdiv_qrnnd(q, r, n1, n0, d) \ |
#define sdiv_qrnnd(q, r, n1, n0, d) \ |
| do { \ |
do { \ |
| union {DItype __ll; \ |
union {DItype __ll; \ |
| struct {SItype __l, __h;} __i; \ |
struct {SItype __l, __h;} __i; \ |
| } __xx; \ |
} __x; \ |
| __xx.__i.__h = n1; __xx.__i.__l = n0; \ |
__x.__i.__h = n1; __x.__i.__l = n0; \ |
| __asm__ ("ediv %3,%2,%0,%1" \ |
__asm__ ("ediv %3,%2,%0,%1" \ |
| : "=g" (q), "=g" (r) \ |
: "=g" (q), "=g" (r) : "g" (__x.__ll), "g" (d)); \ |
| : "g" (__xx.ll), "g" (d)); \ |
|
| } while (0) |
} while (0) |
| |
#if 0 |
| |
/* FIXME: This instruction appears to be unimplemented on some systems (vax |
| |
8800 maybe). */ |
| |
#define count_trailing_zeros(count,x) \ |
| |
do { \ |
| |
__asm__ ("ffs 0, 31, %1, %0" \ |
| |
: "=g" ((USItype) (count)) \ |
| |
: "g" ((USItype) (x))); \ |
| |
} while (0) |
| |
#endif |
| #endif /* __vax__ */ |
#endif /* __vax__ */ |
| |
|
| #if defined (__z8000__) && W_TYPE_SIZE == 16 |
#if defined (__z8000__) && W_TYPE_SIZE == 16 |
| #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \ |
__asm__ ("add %H1,%H5\n\tadc %H0,%H3" \ |
| : "=r" ((unsigned int)(sh)), \ |
: "=r" ((unsigned int)(sh)), "=&r" ((unsigned int)(sl)) \ |
| "=&r" ((unsigned int)(sl)) \ |
: "%0" ((unsigned int)(ah)), "r" ((unsigned int)(bh)), \ |
| : "%0" ((unsigned int)(ah)), \ |
"%1" ((unsigned int)(al)), "rQR" ((unsigned int)(bl))) |
| "r" ((unsigned int)(bh)), \ |
|
| "%1" ((unsigned int)(al)), \ |
|
| "rQR" ((unsigned int)(bl))) |
|
| #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ |
| __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \ |
__asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \ |
| : "=r" ((unsigned int)(sh)), \ |
: "=r" ((unsigned int)(sh)), "=&r" ((unsigned int)(sl)) \ |
| "=&r" ((unsigned int)(sl)) \ |
: "0" ((unsigned int)(ah)), "r" ((unsigned int)(bh)), \ |
| : "0" ((unsigned int)(ah)), \ |
"1" ((unsigned int)(al)), "rQR" ((unsigned int)(bl))) |
| "r" ((unsigned int)(bh)), \ |
|
| "1" ((unsigned int)(al)), \ |
|
| "rQR" ((unsigned int)(bl))) |
|
| #define umul_ppmm(xh, xl, m0, m1) \ |
#define umul_ppmm(xh, xl, m0, m1) \ |
| do { \ |
do { \ |
| union {long int __ll; \ |
union {long int __ll; \ |
| struct {unsigned int __h, __l;} __i; \ |
struct {unsigned int __h, __l;} __i; \ |
| } __xx; \ |
} __x; \ |
| unsigned int __m0 = (m0), __m1 = (m1); \ |
unsigned int __m0 = (m0), __m1 = (m1); \ |
| __asm__ ("mult %S0,%H3" \ |
__asm__ ("mult %S0,%H3" \ |
| : "=r" (__xx.__i.__h), \ |
: "=r" (__x.__i.__h), "=r" (__x.__i.__l) \ |
| "=r" (__xx.__i.__l) \ |
: "%1" (m0), "rQR" (m1)); \ |
| : "%1" (__m0), \ |
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \ |
| "rQR" (__m1)); \ |
|
| (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ |
|
| (xh) += ((((signed int) __m0 >> 15) & __m1) \ |
(xh) += ((((signed int) __m0 >> 15) & __m1) \ |
| + (((signed int) __m1 >> 15) & __m0)); \ |
+ (((signed int) __m1 >> 15) & __m0)); \ |
| } while (0) |
} while (0) |
| Line 1226 extern USItype __udiv_qrnnd (); |
|
| Line 1437 extern USItype __udiv_qrnnd (); |
|
| |
|
| #endif /* __GNUC__ */ |
#endif /* __GNUC__ */ |
| |
|
| |
#endif /* NO_ASM */ |
| |
|
| |
|
| #if !defined (umul_ppmm) && defined (__umulsidi3) |
#if !defined (umul_ppmm) && defined (__umulsidi3) |
| #define umul_ppmm(ph, pl, m0, m1) \ |
#define umul_ppmm(ph, pl, m0, m1) \ |
| { \ |
{ \ |
| Line 1243 extern USItype __udiv_qrnnd (); |
|
| Line 1456 extern USItype __udiv_qrnnd (); |
|
| ((UDWtype) __hi << W_TYPE_SIZE) | __lo; }) |
((UDWtype) __hi << W_TYPE_SIZE) | __lo; }) |
| #endif |
#endif |
| |
|
| |
|
| |
/* Note the prototypes are under !define(umul_ppmm) etc too, since the HPPA |
| |
versions above are different and we don't want to conflict. */ |
| |
|
| |
#if ! defined (umul_ppmm) && HAVE_NATIVE_mpn_umul_ppmm |
| |
#define mpn_umul_ppmm __MPN(umul_ppmm) |
| |
extern mp_limb_t mpn_umul_ppmm _PROTO ((mp_limb_t *, mp_limb_t, mp_limb_t)); |
| |
#define umul_ppmm(wh, wl, u, v) \ |
| |
do { \ |
| |
mp_limb_t __umul_ppmm__p0; \ |
| |
(wh) = __MPN(umul_ppmm) (&__umul_ppmm__p0, \ |
| |
(mp_limb_t) (u), (mp_limb_t) (v)); \ |
| |
(wl) = __umul_ppmm__p0; \ |
| |
} while (0) |
| |
#endif |
| |
|
| |
#if ! defined (udiv_qrnnd) && HAVE_NATIVE_mpn_udiv_qrnnd |
| |
#define mpn_udiv_qrnnd __MPN(udiv_qrnnd) |
| |
extern mp_limb_t mpn_udiv_qrnnd _PROTO ((mp_limb_t *, |
| |
mp_limb_t, mp_limb_t, mp_limb_t)); |
| |
#define udiv_qrnnd(q, r, n1, n0, d) \ |
| |
do { \ |
| |
mp_limb_t __udiv_qrnnd__r; \ |
| |
(q) = mpn_udiv_qrnnd (&__udiv_qrnnd__r, \ |
| |
(mp_limb_t) (n1), (mp_limb_t) (n0), (mp_limb_t) d); \ |
| |
(r) = __udiv_qrnnd__r; \ |
| |
} while (0) |
| |
#endif |
| |
|
| |
|
| /* If this machine has no inline assembler, use C macros. */ |
/* If this machine has no inline assembler, use C macros. */ |
| |
|
| #if !defined (add_ssaaaa) |
#if !defined (add_ssaaaa) |
| Line 1265 extern USItype __udiv_qrnnd (); |
|
| Line 1508 extern USItype __udiv_qrnnd (); |
|
| } while (0) |
} while (0) |
| #endif |
#endif |
| |
|
| |
/* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of |
| |
smul_ppmm. */ |
| |
#if !defined (umul_ppmm) && defined (smul_ppmm) |
| |
#define umul_ppmm(w1, w0, u, v) \ |
| |
do { \ |
| |
UWtype __w1; \ |
| |
UWtype __xm0 = (u), __xm1 = (v); \ |
| |
smul_ppmm (__w1, w0, __xm0, __xm1); \ |
| |
(w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \ |
| |
+ (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \ |
| |
} while (0) |
| |
#endif |
| |
|
| |
/* If we still don't have umul_ppmm, define it using plain C. */ |
| #if !defined (umul_ppmm) |
#if !defined (umul_ppmm) |
| #define umul_ppmm(w1, w0, u, v) \ |
#define umul_ppmm(w1, w0, u, v) \ |
| do { \ |
do { \ |
| Line 1288 extern USItype __udiv_qrnnd (); |
|
| Line 1545 extern USItype __udiv_qrnnd (); |
|
| __x3 += __ll_B; /* yes, add it in the proper pos. */ \ |
__x3 += __ll_B; /* yes, add it in the proper pos. */ \ |
| \ |
\ |
| (w1) = __x3 + __ll_highpart (__x1); \ |
(w1) = __x3 + __ll_highpart (__x1); \ |
| (w0) = (__ll_lowpart (__x1) << W_TYPE_SIZE/2) + __ll_lowpart (__x0);\ |
(w0) = (__x1 << W_TYPE_SIZE/2) + __ll_lowpart (__x0); \ |
| } while (0) |
} while (0) |
| #endif |
#endif |
| |
|
| #if !defined (umul_ppmm) |
/* If we don't have smul_ppmm, define it using umul_ppmm (which surely will |
| |
exist in one form or another. */ |
| |
#if !defined (smul_ppmm) |
| #define smul_ppmm(w1, w0, u, v) \ |
#define smul_ppmm(w1, w0, u, v) \ |
| do { \ |
do { \ |
| UWtype __w1; \ |
UWtype __w1; \ |
| UWtype __m0 = (u), __m1 = (v); \ |
UWtype __xm0 = (u), __xm1 = (v); \ |
| umul_ppmm (__w1, w0, __m0, __m1); \ |
umul_ppmm (__w1, w0, __xm0, __xm1); \ |
| (w1) = __w1 - (-(__m0 >> (W_TYPE_SIZE - 1)) & __m1) \ |
(w1) = __w1 - (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \ |
| - (-(__m1 >> (W_TYPE_SIZE - 1)) & __m0); \ |
- (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \ |
| } while (0) |
} while (0) |
| #endif |
#endif |
| |
|
| Line 1307 extern USItype __udiv_qrnnd (); |
|
| Line 1566 extern USItype __udiv_qrnnd (); |
|
| #define __udiv_qrnnd_c(q, r, n1, n0, d) \ |
#define __udiv_qrnnd_c(q, r, n1, n0, d) \ |
| do { \ |
do { \ |
| UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \ |
UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \ |
| |
\ |
| |
ASSERT ((d) != 0); \ |
| |
ASSERT ((n1) < (d)); \ |
| |
\ |
| __d1 = __ll_highpart (d); \ |
__d1 = __ll_highpart (d); \ |
| __d0 = __ll_lowpart (d); \ |
__d0 = __ll_lowpart (d); \ |
| \ |
\ |
| __r1 = (n1) % __d1; \ |
|
| __q1 = (n1) / __d1; \ |
__q1 = (n1) / __d1; \ |
| |
__r1 = (n1) - __q1 * __d1; \ |
| __m = (UWtype) __q1 * __d0; \ |
__m = (UWtype) __q1 * __d0; \ |
| __r1 = __r1 * __ll_B | __ll_highpart (n0); \ |
__r1 = __r1 * __ll_B | __ll_highpart (n0); \ |
| if (__r1 < __m) \ |
if (__r1 < __m) \ |
| Line 1323 extern USItype __udiv_qrnnd (); |
|
| Line 1586 extern USItype __udiv_qrnnd (); |
|
| } \ |
} \ |
| __r1 -= __m; \ |
__r1 -= __m; \ |
| \ |
\ |
| __r0 = __r1 % __d1; \ |
|
| __q0 = __r1 / __d1; \ |
__q0 = __r1 / __d1; \ |
| |
__r0 = __r1 - __q0 * __d1; \ |
| __m = (UWtype) __q0 * __d0; \ |
__m = (UWtype) __q0 * __d0; \ |
| __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ |
__r0 = __r0 * __ll_B | __ll_lowpart (n0); \ |
| if (__r0 < __m) \ |
if (__r0 < __m) \ |
| Line 1358 extern USItype __udiv_qrnnd (); |
|
| Line 1621 extern USItype __udiv_qrnnd (); |
|
| #endif |
#endif |
| |
|
| #if !defined (count_leading_zeros) |
#if !defined (count_leading_zeros) |
| extern |
|
| #ifdef __STDC__ |
|
| const |
|
| #endif |
|
| unsigned char __clz_tab[]; |
|
| #define count_leading_zeros(count, x) \ |
#define count_leading_zeros(count, x) \ |
| do { \ |
do { \ |
| UWtype __xr = (x); \ |
UWtype __xr = (x); \ |
| UWtype __a; \ |
UWtype __a; \ |
| \ |
\ |
| if (W_TYPE_SIZE <= 32) \ |
if (W_TYPE_SIZE == 32) \ |
| { \ |
{ \ |
| __a = __xr < ((UWtype) 1 << 2*__BITS4) \ |
__a = __xr < ((UWtype) 1 << 2*__BITS4) \ |
| ? (__xr < ((UWtype) 1 << __BITS4) ? 0 : __BITS4) \ |
? (__xr < ((UWtype) 1 << __BITS4) ? 1 : __BITS4 + 1) \ |
| : (__xr < ((UWtype) 1 << 3*__BITS4) ? 2*__BITS4 : 3*__BITS4);\ |
: (__xr < ((UWtype) 1 << 3*__BITS4) ? 2*__BITS4 + 1 \ |
| |
: 3*__BITS4 + 1); \ |
| } \ |
} \ |
| else \ |
else \ |
| { \ |
{ \ |
| for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \ |
for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \ |
| if (((__xr >> __a) & 0xff) != 0) \ |
if (((__xr >> __a) & 0xff) != 0) \ |
| break; \ |
break; \ |
| |
++__a; \ |
| } \ |
} \ |
| \ |
\ |
| (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \ |
(count) = W_TYPE_SIZE + 1 - __a - __clz_tab[__xr >> __a]; \ |
| } while (0) |
} while (0) |
| /* This version gives a well-defined value for zero. */ |
/* This version gives a well-defined value for zero. */ |
| #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE |
#define COUNT_LEADING_ZEROS_0 (W_TYPE_SIZE - 1) |
| |
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB |
| #endif |
#endif |
| |
|
| |
#ifdef COUNT_LEADING_ZEROS_NEED_CLZ_TAB |
| |
extern const unsigned char __GMP_DECLSPEC __clz_tab[128]; |
| |
#endif |
| |
|
| #if !defined (count_trailing_zeros) |
#if !defined (count_trailing_zeros) |
| /* Define count_trailing_zeros using count_leading_zeros. The latter might be |
/* Define count_trailing_zeros using count_leading_zeros. The latter might be |
| defined in asm, but if it is not, the C version above is good enough. */ |
defined in asm, but if it is not, the C version above is good enough. */ |
| Line 1394 unsigned char __clz_tab[]; |
|
| Line 1659 unsigned char __clz_tab[]; |
|
| do { \ |
do { \ |
| UWtype __ctz_x = (x); \ |
UWtype __ctz_x = (x); \ |
| UWtype __ctz_c; \ |
UWtype __ctz_c; \ |
| |
ASSERT (__ctz_x != 0); \ |
| count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \ |
count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \ |
| (count) = W_TYPE_SIZE - 1 - __ctz_c; \ |
(count) = W_TYPE_SIZE - 1 - __ctz_c; \ |
| } while (0) |
} while (0) |
| Line 1401 unsigned char __clz_tab[]; |
|
| Line 1667 unsigned char __clz_tab[]; |
|
| |
|
| #ifndef UDIV_NEEDS_NORMALIZATION |
#ifndef UDIV_NEEDS_NORMALIZATION |
| #define UDIV_NEEDS_NORMALIZATION 0 |
#define UDIV_NEEDS_NORMALIZATION 0 |
| |
#endif |
| |
|
| |
/* Whether udiv_qrnnd is actually implemented with udiv_qrnnd_preinv, and |
| |
that hence the latter should always be used. */ |
| |
#ifndef UDIV_PREINV_ALWAYS |
| |
#define UDIV_PREINV_ALWAYS 0 |
| |
#endif |
| |
|
| |
/* Give defaults for UMUL_TIME and UDIV_TIME. */ |
| |
#ifndef UMUL_TIME |
| |
#define UMUL_TIME 1 |
| |
#endif |
| |
|
| |
#ifndef UDIV_TIME |
| |
#define UDIV_TIME UMUL_TIME |
| #endif |
#endif |
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